ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 129

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BSD DATA RECEPTION
To receive data, the LIN/BSD peripheral must first be con-
figured in BSD mode where LHSCON[6] = 1. In this mode,
LHSCON0[8] should be set to ensure that the LHS break timer
(see the LIN Hardware Break Timer1 Register section) generates
an interrupt on the rising edge of the BSD bus.
The LHS break timer is cleared and starts counting on the falling
edge of the BSD bus; the timer is subsequently stopped and
generates an interrupt on the rising edge of the BSD bus. Given
that the LHS break timer is clocked by the low power 131 kHz
oscillator, the value in LHSVAL1 can be interpreted by user code
to determine if the received data bit is a BSD sync pulse, 0, or 1.
1
LHSVAL1 CLEARED
AND STARTS COUNTING
ON THIS EDGE
BSD PERIOD
IN 0 STATE
RECEIVE SECOND
RECEIVE DATA
FROM MASTER
Figure 56. BSD Slave Node State Machine
PARITY BIT
Figure 57. Master Transmit, Slave Read
SYNCHRONIZATION
2
INITIALIZE BSD
RECEIVE FIRST
HARDWARE/
LHSVAL1 STOPPED
AND GENERATES
INTERRUPT ON THIS EDGE
SOFTWARE
DIRECTION
PARITY BIT
ACK/NACK
REGISTER
TRANSMIT
ADDRESS
ADDRESS
RECEIVE
RECEIVE
RECEIVE
RECEIVE
PULSES
SLAVE
BIT
BSD PERIOD
IN 1 STATE
TRANSMIT SECOND
TRANSMIT DATA
TO MASTER
PARITY BIT
Rev. B | Page 129 of 136
BSD DATA TRANSMISSION
User code forces the GPIO_12 signal low for a specified time to
transmit data in BSD mode. In addition, user code uses the sync
timer (LHSVAL0), the LHS sync capture register (LHSCAP), and
the LHS sync compare register (LHSCMP) to determine the time
that the BSD bus should be held low for bit transmissions in the
0 or 1 state.
As described in the BSD Example Pulse Widths section, even
when the slave is transmitting data, the master always starts the
bit transmission period by pulling the BSD bus low. If BSD
mode is selected (LHSCON0[6] = 1), the LIN sync timer value
is captured in LHSCAP on every falling edge of the BSD bus.
The LIN sync timer runs continuously in BSD mode.
Then, user code can immediately force GPIO_12 low and read the
captured timer value from LHSCAP. Next, the user can calculate
how many clock periods (with a 5 MHz clock) should elapse before
the GPIO_12 is driven high for a pulse width in the 0 or 1 state.
The calculated number can be added to the LHSCAP value and
written into the LHSCMP register. If LHSCON0[5] is set, the sync
timer, which continues to count (being clocked by a 5 MHz clock),
eventually equals the LHSCMP value and generates an LHS
compare interrupt (LHSSTA[3]).
The response to this interrupt should be to force the GPIO_12
signal and therefore the BSD bus high. The software control
of the GPIO_12 signal, along with the correct use of the LIN
synchronization timers, ensures that valid pulse widths in the
0 and 1 states can be transmitted from the ADuC7034, as shown
in Figure 58. However, care needs to be taken if switching from
BSD write mode to BSD read mode, as described in Table 92
(see the LHSCON0[8] bit).
WAKE UP FROM BSD INTERFACE
The MCU core can be woken up from power-down via the BSD
physical interface. Before entering power-down mode, user
code should enable the start condition interrupt (LHSCON0[3]).
When this interrupt is enabled, a high-to-low transition on the
LIN/BSD pin generates an interrupt event and wakes up the
MCU core.
2
1
LHSVAL0 LOADED
INTO LHSCAP HERE
MASTER DRIVES
BSD BUS LOW
BSD PERIOD
IN 0 STATE
Figure 58. Master Read, Slave Transmit
3
4
SOFTWARE ASSERTS
BSD LOW HERE
LHSCMP = LHSVAL0
INTERRUPT GENERATED
HERE
5
SOFTWARE DEASSERTS
BSD HIGH HERE
BSD PERIOD
IN 1 STATE
ADuC7034