ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 77

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timer1 Capture Register
Name:
Address:
Default Value:
Access:
Function:
Table 53. T1CON MMR Bit Designations
Bit
31 to 24
23
22 to 20
19
18
17
16 to 12
11 to 9
8
7
6
5 to 4
3 to 0
T1CAP
0xFFFF0330
0x00000000
Read only
This 32-bit register holds the 32-bit value
captured by an enabled IRQ event.
Set to select interrupt generation from the postscaler counter.
Cleared to select interrupt generation directly from Timer1.
00 = binary (default).
01 = reserved.
10 = hours:minutes:seconds:hundredths (23 hours to 0 hours).
11 = hours:minutes:seconds:hundredths (255 hours to 0 hours).
0000 = source clock/1 (default).
0100 = source clock/16.
1000 = source clock/256.
1111 = source clock/32,768.
Description
8-bit postscaler.
By writing to these eight bits, a value is written to the postscaler. Writing 0 is interpreted as a 1.
By reading these eight bits, the current value of the counter is read.
Timer1 enable postscaler.
Set to enable the Timer1 postscaler.
Cleared to disable the Timer1 postscaler.
Reserved. These bits are reserved and should be written as 0 by user code.
Postscaler compare flag. Read only.
Set if the number of Timer1 overflows is equal to the number written to the postscaler.
Timer1 interrupt source.
Event select bit.
Set by user to enable time capture of an event.
Cleared by user to disable time capture of an event.
Event number (0 to 17). The events are defined in Table 51.
Clock select.
000 = core clock (default).
001 = low power 32.768 kHz oscillator.
010 = GPIO_8.
011 = GPIO_5.
Count up.
Set by user for Timer1 to count up.
Cleared by user for Timer1 to count down (default).
Timer1 enable bit.
Set by user to enable Timer1.
Cleared by user to disable Timer1 (default).
Timer1 mode.
Set by user to operate in periodic mode.
Cleared by user to operate in free running mode (default).
Format.
Prescaler.
Rev. B | Page 77 of 136
Timer1 Control Register
Name:
Address:
Default Value:
Access:
Function:
T1CON
0x01000000
Read/write
This 32-bit MMR configures the mode of
operation for Timer1.
0xFFFF0328
ADuC7034