ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 118

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7034
LIN Hardware Synchronization Status Register
Name:
Address:
Default Value:
Access:
Function:
Table 91. LHSSTA MMR Bit Designations
Bit
7
6
5
4
3
2
1
0
LHSSTA
0x00
Read only
The LHS status register is an 8-bit register whose bits reflect the current operating status of the LIN interface.
0xFFFF0780
Description
Reserved. These read only bits are reserved for future use.
Rising edge detected (BSD mode only).
Set to 1 by hardware to indicate a rising edge has been detected on the BSD bus.
Cleared to 0 after user code reads the LHSSTA MMR.
LHS reset complete flag.
Set to 1 by hardware to indicate a LHS reset command has completed successfully.
Cleared to 0, after user code reads the LHSSTA MMR.
Break field error.
Set to 1 by hardware and generates an LHS interrupt (IRQEN[7]) when the 12-bit break timer (LHSVAL1) register
overflows to indicate the LIN bus has stayed low too long, thus suggesting a possible LIN bus error.
Cleared to 0 after user code reads the LHSSTA MMR.
LHS compare interrupt.
Set to 1 by hardware when the value in LHSVAL0 (LIN synchronization bit timer) equals the value in the LHSCMP register.
Cleared to 0 after user code reads the LHSSTA MMR.
Stop condition interrupt.
Set to 1 by hardware when a stop condition is detected.
Cleared to 0 after user code reads LHSSTA MMR.
Start condition interrupt.
Set to 1 by hardware when a start condition is detected.
Cleared to 0 after user code reads LHSSTA MMR.
Break timer compare interrupt.
Set to 1 by hardware when a valid LIN break condition is detected. A LIN break condition is generated when the LIN
break timer value reaches the break timer compare value (see LHSVAL1 in the LIN Hardware Break Timer1 Register
section for more information).
Cleared to 0 after user code reads the LHSSTA MMR.
Rev. B | Page 118 of 136