H27US08121B-TPCB HYNIX SEMICONDUCTOR, H27US08121B-TPCB Datasheet - Page 21

• Manufacturer Part Number: H27US08121B-TPCB
• Description: MEMORY, FLASH NAND 512MB, TSOP48
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H27US08121B-TPCB

• Memory Size: 512Mbit
• Access Time: 45ns
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: 0°C To +70°C
• Package / Case: TSOP
• Base Number: 27
• Memory Type: Flash - NAND
• Memory Configuration: 64M X 8, 32M X 16
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6: Status Register Bit
Read Electronic Signature
The device contains a Manufacturer Code and Device Code. To read these codes two steps are required:
1. first use one Bus Write cycle to issue the Read Electronic Signature command (90h)
2. then subsequent Bus Read operations will read the Manufacturer Code and the Device Code until another command
Refer to Table, Read Electronic Signature for information on the addresses.
Automatic Page 0 Read at Power-Up
Automatic Page 0 Read at Power-Up is an option available on all devices belonging to the NAND Flash 528 Byte/264
Word Page family. It allows the microcontroller to directly download boot code from page 0, without requiring any
command or address input sequence. The Automatic Page 0 Read option is particularly suited for applications that
boot from the NAND.
Devices delivered with Automatic Page 0 Read at Power-Up can have the Sequential Row Read option either enabled
ordisabled.
Automatic Page 0 Read Description.
At powerup, once the supply voltage has reached the threshold level, V
state and the internal NAND device functions (reading, writing, erasing) are enabled.
The device then automatically switches to read mode where, as in any read operation, the device is busy for a time
t
High. The data can then be read out sequentially on the I/O bus by pulsing the Read Enable, RE#, signal. Figures 18
and 19 show the power-up waveforms for devices featuring the Automatic Page 0 Read option.
Rev 0.6 / Oct. 2004
BLBH1
is issued.
SR4, SR3, SR2
during the data is transferred to the Page Buffer. Once the data transfer is complete the Ready/Busy signal goes
HY27US08121M
HY27SS08121M
HY27US16121M
HY27SS16121M
Part Number
SR7
SR6
SR5
SR0
Bit
Program/ Erase/ Read
Program/Erase/Read
Write Protection
Generic Error
Controller
Controller
Reserved
NAME
Manufacture Code
00ADh
00ADh
ADh
ADh
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Logic Level
Don
'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
t Care
Device Code
0056h
0046h
CCth
76h
36h
Not Protected
Protected
P/E/R C Inactive, device ready
P/E/R C active, device busy
P/E/R C inactive, device ready
P/E/R C active, device busy
Error - Operation failed
No Error - Operation successful
HY27US(08/16)121M Series
HY27SS(08/16)121M Series
, all digital outputs revert to their reset
Definition
Bus Width
x16
x16
x8
x8
21