H27US08121B-TPCB HYNIX SEMICONDUCTOR, H27US08121B-TPCB Datasheet - Page 18

• Manufacturer Part Number: H27US08121B-TPCB
• Description: MEMORY, FLASH NAND 512MB, TSOP48
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H27US08121B-TPCB

• Memory Size: 512Mbit
• Access Time: 45ns
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: 0°C To +70°C
• Package / Case: TSOP
• Base Number: 27
• Memory Type: Flash - NAND
• Memory Configuration: 64M X 8, 32M X 16
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I/O
Copy Back Program
The Copy Back Program operation is used to copy the data stored in one page and reprogram it in another page.
The Copy Back Program operation does not require external memory and so the operation is faster and more efficient
because the reading and loading cycles are not required. The operation is particularly useful when a portion of a block
is updated and the rest of the block needs to be copied to the newly assigned block.
If the Copy Back Program operation fails an error is signalled in the Status Register. However as the standard external
ECC cannot be used with the Copy Back operation bit error due to charge loss cannot be detected. For this reason it is
recommended to limit the number of Copy Back operations on the same data and/or to improve the performance of
the ECC.
The Copy Back Program operation requires three steps:
4 bus write cycles to input the source page address). This operation copies all 264 Words/ 528 Bytes from the page
into the Page Buffer.
given with the 4 bus cycles to input the target page address.
After a Copy Back Program operation, a partial page program is not allowed in the target page until the block has been
erased.
See Figure 15 for an example of the Copy Back operation.
RB
Block Erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the addressed block to '1'. All
previous data in the block is lost. An erase operation consists of three steps (refer to Figure 17):
1. One bus cycle is required to setup the Block Erase command.
2. Only three bus cycles for 512Mb devices are required to input the block address. The first cycle (A0 to A7) is not
required as only addresses A14 to A25 (highest address depends on device density) are valid, A9 to A13 are ignored.
In the last address cycle I/O
3. One bus cycle is required to issue the confirm command to start the P/E/R Controller.
Rev 0.6 / Oct. 2004
- 1. The source page must be read using the Read A command (one bus write cycle to setup the command and then
- 2. When the device returns to the ready state (Ready/Busy High), the second bus write cycle of the command is
- 3. Then the confirm command is issued to start the P/E/R Controller.
Read
00h
Code
(Read Busy time)
Address Inputs
Source
tBLBH1
0
to I/O
7
must be set to V
Figure 15. Copy Back Operation
Copy Back
Code
8Ah
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
IL
.
Address Inputs
(Program Busy time)
A25
Target
must be the same for the Source and Target Pages.
tBLBH2
HY27US(08/16)121M Series
HY27SS(08/16)121M Series
10h
Busy
Read Status Register
70h
SR0
18