H27US08121B-TPCB HYNIX SEMICONDUCTOR, H27US08121B-TPCB Datasheet - Page 16

• Manufacturer Part Number: H27US08121B-TPCB
• Description: MEMORY, FLASH NAND 512MB, TSOP48
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H27US08121B-TPCB

• Memory Size: 512Mbit
• Access Time: 45ns
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: 0°C To +70°C
• Package / Case: TSOP
• Base Number: 27
• Memory Type: Flash - NAND
• Memory Configuration: 64M X 8, 32M X 16
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I/O
RB
Rev 0.6 / Oct. 2004
Block
Block
Block
Block
Block
Block
Block
Block
01h/50h
Command
00h/
(1
(1
(1
(1
Code
(1
(1
(1
(1
st
st
st
st
st
st
st
st
Area A
Area A
Area A
Area A
half Page)
half Page)
half Page)
half Page)
Area A
Area A
Area A
Area A
half Page)
half Page)
half Page)
half Page)
Read A Command, x8 Devices
Read A Command, x8 Devices
Read A Command, x8 Devices
Read B Command, x8 Devices
Read B Command, x8 Devices
Read B Command, x8 Devices
(Read Busy time)
Address Inputs
(2
(2
(2
(2
(2
(2
nd
nd
nd
nd
nd
nd
Area B
Area B
Area B
Area B
Area B
Area B
half Page) (Spare)
half Page) (Spare)
half Page) (Spare)
half Page)
half Page)
half Page)
Figure 13. Sequential Row Read Block Diagrams
tBLBH1
Figure 12. Sequential Row Read Operation
(Spare)
(Spare)
(Spare)
Busy
Area C
Area C
Area C
Area C
Area C
Area C
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Page Output
1
1
1
1
2
2
2
2
N
N
N
N
1
1
1
1
2
2
2
2
N
N
N
N
st
st
st
st
nd
nd
nd
nd
th
th
th
th
st
st
st
st
nd
nd
nd
nd
th
th
th
th
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
1st
Block
Block
Block
Block
Block
Block
Block
Block
tBLBH1
Busy
Area A
Area A
Area A
Read C Command, x8/x16 Devices
Read C Command, x8/x16 Devices
Read C Command, x8/x16 Devices
Read A Command, x16 Devices
Read A Command, x16 Devices
Read A Command, x16 Devices
HY27US(08/16)121M Series
HY27SS(08/16)121M Series
(main area)
(main area)
(main area)
Page Output
Area A
Area A
Area A
2nd
tBLBH1
Area A/B
Area A/B
Area A/B
Busy
(Spare)
(Spare)
(Spare)
(Spare)
(Spare)
(Spare)
Area C
Area C
Area C
Area C
Area C
Area C
Page Output
Nth
1
1
1
2
2
2
N
N
N
1
1
1
1
2
2
2
2
N
N
N
N
st
st
st
nd
nd
nd
th
th
th
st
st
st
st
nd
nd
nd
nd
th
th
th
th
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
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