UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 924
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UPD78F1001GA-HAA-AX
Manufacturer Part Number
UPD78F1001GA-HAA-AX
Description
MCU 16BIT 78K0R/KX3-L 44-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GA-HAA-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GA-HAA-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 924 of 1171
- Download datasheet (8Mb)
78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Notes 1. The P140 pin is not mounted onto 40-pin and 44-pin products of the 78K0R/KC3-L.
Caution A watchdog timer internal reset resets the watchdog timer.
(when X1 oscillation is selected)
(when X1 oscillation is selected)
Figure 21-3. Timing of Reset Due to Execution of Illegal Instruction or Watchdog Timer Overflow
2. Read P140 as P130 if using the 78K0R/KF3-L or 78K0R/KG3-L.
3. When P140 is set to high-level output before reset is effected, the output signal of P140 can be dummy-
High-speed system clock
High-speed system clock
output as a reset signal to an external device, because P140 outputs a low level when reset is effected. To
release a reset signal to an external device, set P140 to high-level output by software.
(except P140
(except P140
Internal reset signal
Execution of Illegal
Internal reset signal
Internal high-speed
Internal high-speed
Watchdog timer
oscillation clock
oscillation clock
(P140
(P140
CPU status
CPU status
Instruction/
overflow
RESET
Port pin
Port pin
Port pin
Port pin
Notes 1, 2
Notes 1, 2
Notes 1, 2
Notes 1, 2
)
)
)
)
Normal operation
Normal operation
Figure 21-2. Timing of Reset by RESET Input
Delay
(oscillation stop)
Reset period
Reset period
accuracy stabilization
accuracy stabilization
Wait for oscillation
Wait for oscillation
Reset processi n g
(195 to 341 s)
Note 3
Note 3
Hi-Z
Hi-Z
μ
Reset processing (2.12 to 5.84 ms)
CHAPTER 21 RESET FUNCTION
Starting X1 oscillation is specified by software.
Starting X1 oscillation is specified by software.
Normal operation
(internal high-speed oscillation clock)
Normal operation
(internal high-speed oscillation clock)
924
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