UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 167

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note Those are only mounted in the 78K0R/KF3-L (
78K0R/Kx3-L
Address Special Function Register (SFR) Name
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
F0017H
F0030H
F0031H
F0033H
F0034H
F0035H
F0036H
F0037H
F0038H
F0039H
F003BH Pull-up resistor option register
F003CH Pull-up resistor option register
F003DH Pull-up resistor option register
F003EH Pull-up resistor option register
F0040H
F0041H
F0043H
F0047H
F0048H
F004EH Port input mode register 14
F0050H
F0051H
F0053H
F0057H
F005EH Port output mode register 14
F0060H
F0061H
F0062H
F00E0H Multiplication/division data
F00E2H Multiplication/division data
F00E8H Multiplication/division control
F00F0H Peripheral enable register 0
F00F1H Peripheral enable register 1
F00F2H Peripheral enable register 2
78F1030).
A/D port configuration register
Pull-up resistor option register 0 PU0
Pull-up resistor option register 1 PU1
Pull-up resistor option register 3 PU3
Pull-up resistor option register 4 PU4
Pull-up resistor option register 5 PU5
Pull-up resistor option register 6 PU6
Pull-up resistor option register 7 PU7
Pull-up resistor option register 8 PU8
Pull-up resistor option register 9 PU9
11
12
13
14
Port input mode register 0
Port input mode register 1
Port input mode register 3
Port input mode register 7
Port input mode register 8
Port output mode register 0
Port output mode register 1
Port output mode register 0
Port output mode register 1
Noise filter enable register 0
Noise filter enable register 1
Noise filter enable register 2
register C (L)
register C (H)
register
Table 4-6. Extended SFR (2nd SFR) List (1/8)
ADPC
PU11
PU12
PU13
PU14
PIM0
PIM1
PIM3
PIM7
PIM8
PIM14
POM0
POM1
POM3
POM7
POM14
NFEN0
NFEN1
NFEN2
MDCL
MDCH
MDUC
PER0
PER1
PER2
Symbol
μ
PD78F1027 and 78F1028) and the 78K0R/KG3-L (
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Manipulable Bit Range
1-bit
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
√
√
√
√
8-bit
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
√
√
√
√
16-bit
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
√
√
−
−
−
−
CHAPTER 4 CPU ARCHITECTURE
After Reset
0000H
0000H
10H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
√
−
√
√
√
√
−
√
−
−
−
√
−
−
−
−
√
√
√
−
−
−
√
√
−
√
√
√
√
√
√
√
√
√
√
−
√
√
√
√
−
√
−
−
−
√
−
−
−
−
√
√
√
−
−
−
√
√
−
√
√
√
√
√
√
√
√
√
μ
PD78F1029 and
√
−
√
√
√
√
−
√
−
−
−
√
−
−
−
−
√
√
√
−
−
−
√
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
−
−
−
√
−
−
−
−
√
√
√
−
−
−
√
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
−
−
−
√
−
√
−
−
√
√
√
−
−
−
√
√
−
√
√
√
√
√
√
√
√
√
Note Note
√
√
√
√
√
√
√
√
−
√
√
√
−
√
√
√
−
−
−
√
√
√
−
−
√
√
√
√
√
√
√
√
−
167
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
√
√
√
−
−
√
√
√
√
√
√
√
√
−