UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 730
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UPD78F1001GA-HAA-AX
Manufacturer Part Number
UPD78F1001GA-HAA-AX
Description
MCU 16BIT 78K0R/KX3-L 44-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GA-HAA-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GA-HAA-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(1) Register setting
Figure 14-102. Example of Contents of Registers for Data Transmission of Simplified I
SMRmn
SCRmn
SDRmn
SOEm
SOm
(a) Serial mode register mn (SMRmn) … Do not manipulate this register during data
(b) Serial communication operation setting register mn (SCRmn) … Do not manipulate the bits of this
(d) Serial output register m (SOm) … Do not manipulate this register during data
(e) Serial output enable register m (SOEm) … Do not manipulate this register during data
Notes 1. Serial array unit 0 only.
Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), r: IIC number (r = 10, 20)
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOr)
2. The value varies depending on the communication data during communication operation.
CKSmn
TXEmn
0/1
15
15
15
15
15
1
0
0
2.
CCSmn
RXEmn
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 02, r = 10
78K0R/KF3-L, 78K0R/KG3-L:
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
14
14
14
14
14
0
0
0
0
: Setting is fixed in the CSI master transmission mode,
DAPmn
13
13
13
13
13
0
0
0
0
Baud rate setting
CKPmn
12
12
12
12
12
0
0
0
0
11
11
11
11
11
0
0
1
0
EOCmn
CKOm2
Notes 1, 2
0/1
10
10
10
10
10
0
0
0
transmission/reception.
transmission/reception.
PTCmn1
CKOm1
Note 1
0
9
0
9
9
×
0
9
9
transmission/reception.
PTCmn0
CKOm0
STSmn
0/1
Note 2
8
0
8
0
8
8
0
8
0
DIRmn
0
0
0
7
7
7
7
7
0
mn = 02, 10, r = 10, 20
SISmn0
0
0
6
6
6
0
0
6
6
SLCmn1
5
1
5
0
5
0
5
5
0
CHAPTER 14 SERIAL ARRAY UNIT
: Setting disabled (set to the initial value)
register, except the TXEmn and
RXEmn bits, during data
transmission/reception.
Transmit data setting
SLCmn0
SIOr
0
4
1
0
4
4
4
4
0
0
0
1
3
3
3
0
3
3
DLSmn2
0/1
MDmn2
SOEm2
SOm2
0/1
2
1
2
1
2
2
2
2
Note 2
C (IIC10, IIC20)(1/2)
MDmn1
DLSmn1
SOEm1
SOm1
×
Note 1
0
1
1
Note 1
1
1
1
1
×
MDmn0
DLSmn0
0/1
SOEm0
SOm0
0/1
0
1
0
0
0
0
0
Note 2
730
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