UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 686

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Notes 1. When changing the clock selected for f
Remarks 1. X: Don’t care
Register
SMRmn
CKSmn
0
1
2.
3.
do so after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial
array unit (SAU). When selecting INTTM02 for the operation clock, also stop the timer array unit 0 (timer
channel stop register 0 (TT0) = 00FFH).
SAU0 can be operated at a fixed division ratio of the subsystem clock, regardless of the f
(main system clock, sub system clock), by operating the interval timer for which f
selected as the count clock (setting the TIS02 bit of timer input select register 0 (TIS0) to 1) and
selecting INTTM02 by using the SPS0 register in channel 2 of TAU0. When changing f
SAU0 and TAU0 must be stopped as described in Note 1 above.
The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
PRS
m13
2. m: Unit number (m = 0 to 2), n: Channel number (n = 0 to 2)
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L (
78K0R/KF3-L (
78K0R/KG3-L (
78K0R/KG3-L (
PRS
m12
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
Table 14-2. Selection of Operation Clock For 3-Wire Serial I/O
Other than above
PRS
m11
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
1
SPSm Register
μ
μ
PRS
m10
μ
μ
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
1
PD78F1010, 78F1011, 78F1012):
PD78F1027, 78F1028):
PD78F1013, 78F1014):
PD78F1029, 78F1030):
PRS
m03
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
PRS
m02
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
PRS
m01
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
1
CLK
(by changing the system clock control register (CKC) value),
PRS
m00
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
1
f
f
f
f
f
f
f
f
f
f
f
f
INTTM02 if m = 0
f
f
f
f
f
f
f
f
f
f
f
f
INTTM02 if m = 0
Setting prohibited
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
2
3
4
5
6
7
8
9
10
11
2
3
4
5
6
7
8
9
10
11
mn = 00 to 02
mn = 00 to 02, 10
mn = 00 to 02, 10, 20, 21
mn = 00 to 02, 10
mn = 00 to 02, 10, 20, 21
CHAPTER 14 SERIAL ARRAY UNIT
Operation Clock (f
Note 2
Note 2
, setting prohibited if m = 1
, setting prohibited if m = 1
20 MHz
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.77 kHz
20 MHz
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.77 kHz
MCK
f
CLK
)
Note 1
= 20 MHz
SUB
/4
Note 3
CLK
CLK
, however,
frequency
has been
686