UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 834
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UPD78F1001GA-HAA-AX
Manufacturer Part Number
UPD78F1001GA-HAA-AX
Description
MCU 16BIT 78K0R/KX3-L 44-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GA-HAA-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GA-HAA-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(1) Start condition ~ address ~ data
Notes 1. To cancel master wait, write “FFH” to IICA or set the WREL bit.
(communication status)
(communication status)
(8 or 9 clock wait)
(8 or 9 clock wait)
(wait cancellation)
(wait cancellation)
(transmit/receive)
(transmit/receive)
(ACK detection)
(ACK detection)
(ST detection)
(SP detection)
(ACK control)
(ACK control)
Master side
(ST trigger)
(SP trigger)
SDA0 (bus)
Slave side
(data line)
(interrupt)
SCL0 (bus)
(interrupt)
(clock line)
INTIICA
Bus line
INTIICA
2. Make sure that the time between the fall of the SDA0 pin signal and the fall of the SCL0 pin signal is at
3. Write data to IICA, not setting the WREL bit, in order to cancel a wait state during slave transmission.
WTIM
MSTS
WREL
WTIM
WREL
ACKD
ACKE
ACKD
ACKE
MSTS
SPD
IICA
SPT
TRC
IICA
STD
TRC
STT
(When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3)
least 4.0
H
<1>
L
H
H
L
L
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
μ
s when specifying standard mode and at least 0.6
Figure 15-33. Example of Slave to Master Communication
Note 2
<2>
AD6
Start condition
AD5
AD4
Slave address
AD3
AD2
CHAPTER 15 SERIAL INTERFACE IICA
AD1
μ
AD0
s when specifying fast mode.
R
<3>
ACK
<6>
<4>
<5>
Note 3
<7>
D
1
7
Note 1
834
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