UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 382

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(11) CPU clock changing from subsystem clock (D) to high-speed system clock (C) (products other than
(12) CPU clock changing from 20 MHz internal high-speed oscillation clock (J) to internal high-speed oscillation
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(Setting sequence of SFR registers)
Status Transition
(J) → (B)
Status Transition
(D) → (C) (external main
clock)
(D) → (C) (X1 clock: 2 MHz ≤
f
(D) → (C) (X1 clock: 10 MHz <
f
X
X
≤ 10 MHz)
≤ 20 MHz)
Notes 1.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
Remark (A) to (K) in Table 7-4 correspond to (A) to (K) in Figure 7-19.
78K0R/KC3-L (40-pin))
clock (B)
Setting Flag of SFR Register
2. FSEL = 1 when f
(Setting sequence of SFR registers)
CHAPTER 30 ELECTRICAL SPECIFICATIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L) or
CHAPTER 31 ELECTRICAL SPECIFICATIONS (78K0R/KF3-L, 78K0R/KG3-L)).
Set the oscillation stabilization time as follows.
If a divided clock is selected and f
• Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time ≤
Setting Flag of SFR Register
Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
Table 7-4. CPU Clock Transition and SFR Register Setting Examples (5/6)
CLK
Unnecessary if the CPU is operating with the high-speed
Register
Note 1
Note 1
Note 1
OSTS
> 10 MHz
CSC Register
MSTOP
CLK
0
0
0
system clock
≤ 10 MHz, use with FSEL = 0 is possible even if f
SELDSC
Register
OSMC
0
FSEL
1
0/1
Note 2
0
DSCCTL Register
Must not be
Register
checked
checked
checked
Must be
Must be
OSTC
CHAPTER 7 CLOCK GENERATOR
registers are already set
MCM0
Unnecessary if these
1
1
1
DSCON
CKC Register
0
X
> 10 MHz.
CSS
0
0
0
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