UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 407

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07)
(3) Timer mode register mn (TMRmn)
TMRmn
Symbol
The TMRmn register sets an operation mode of channel n. It is used to select an operation clock (f
clock, whether the timer operates as the master or a slave, a start trigger and a capture trigger, the valid edge of
the timer input, and an operation mode (interval, capture, event counter, one-count, or capture & one-count).
Rewriting the TMRmn register is prohibited when the register is in operation (when TEmn = 1). However, bits 7 and
6 (CISmn1, CISmn0) can be rewritten even while the register is operating with some functions (when TEmn = 1)
(for details, see 8.7 Independent Channel Operation Function of Timer Array Unit and 8.8 Simultaneous
Channel Operation Function of Timer Array Unit.
The TMRmn register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Cautions 1. Be sure to clear bits 14, 13, 5, and 4 to “0”.
Note The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
F01C8H, F01C9H (TMR10) to F01CEH, F01CFH (TMR13)
Operation clock (f
depending on the setting of the CCSmn bit.
Count clock (f
CKS
CCS
CKS
mn
mn
mn
15
0
1
0
1
2. The timer array unit must be stopped (TTm = 00FFH) if the clock selected for f
However, in case of the timer input pin (TImn), mn changes as below.
78K0R/KC3-L (40-pin):
78K0R/KC3-L (44-pin, 48-pin):
78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L, 78K0R/KG3-L:
Operation clock CKm0 set by timer clock select register m (TPSm)
Operation clock CKm1 set by timer clock select register m (TPSm)
Operation clock (f
Valid edge of input signal input from the TImn pin/subsystem clock divided by 4 (f
(by changing the value of the system clock control register (CKC)), even if the operating clock
specified by using the CKSmn bit (f
or the subsystem clock divided by 4 (f
14
0
TCLK
Figure 8-11. Format of Timer Mode Register mn (TMRmn) (1/3)
13
0
) is used for the timer/counter, output controller, and interrupt controller.
MCK
) is used by the edge detector. A count clock (f
CCS
mn
12
MCK
) specified by the CKSmn bit
MAST
ERmn
11
STS
mn2
10
Selection of operation clock (f
Selection of count clock (f
STS
mn1
mn = 02 to 07
mn = 00 to 07
mn = 00 to 07
mn = 00 to 07, 10 to 13
9
STS
mn0
MCK
8
SUB
After reset: 0000H
), the valid edge of the signal input from the TImn pin,
/4) is selected as the count clock (f
mn1
CIS
7
TCLK
mn0
CIS
MCK
6
TCLK
) of channel n
) of channel n
) and a sampling clock are generated
CHAPTER 8 TIMER ARRAY UNIT
5
0
R/W
4
0
SUB
mn3
MD
3
/4)
Note
mn2
MD
2
TCLK
mn1
CLK
MD
).
1
MCK
is changed
), a count
mn0
MD
0
407