UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 572

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(2) Scan mode
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
A/D conversion
The four analog input channels of scans 0 to 3, which are specified by the analog input channel specification register
(ADS), while the ADMD bit of the A/D converter mode register (ADM) is 1, are A/D converted successively. A/D
conversion is performed in sequence, starting from the analog input channel specified by scan 0.
When A/D conversion of one analog input is complete, the conversion result is stored in the A/D conversion result
register (ADCR) and the A/D conversion end interrupt request signal (INTAD) is generated.
The A/D conversion results of all the analog input channels are stored in the ADCR register.
recommended to save the contents of the ADCR register to RAM, once A/D conversion of one analog input channel
has been completed.
After A/D conversion has been completed, A/D conversion is repeated successively, unless the ADCS bit is set to 0.
If anything is written to the ADM or ADS register during conversion, A/D conversion is aborted. In this case, A/D
conversion is started again from the analog input channel of scan 0.
operation
ADCRH
ADCR,
INTAD
ANI0
ANI1
ANI2
ANI3
Conversion start
Set ADCS bit = 1
Data 1
Data 1
(ANI0)
Figure 13-15. Example of Scan Mode Operation Timing
Data 1
(ANI0)
Data 2
Data 2
(ANI1)
Data 2
(ANI1)
Data 3
Data 3
(ANI2)
Data 3
(ANI2)
Data 4
Data 4
(ANI3)
Data 5
Data 4
(ANI3)
Data 5
(ANI0)
Data 5
(ANI0)
Data 6
Data 6
(ANI1)
CHAPTER 13 A/D CONVERTER
Data 6
(ANI1)
Data 7
Data 7
(ANI2)
Data 7
(ANI2)
Data 8
Data 8
(ANI3)
Conversion stop
Set ADCS bit = 0
It is therefore
Data 8
(ANI3)
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