UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 785

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
15.5.8 Interrupt request (INTIICA) generation timing and wait control
and the corresponding wait control, as shown in Table 15-2.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The setting of bit 3 (WTIM) of IICA control register 0 (IICCTL0) determines the timing by which INTIICA is generated
Notes 1. The slave device’s INTIICA signal and wait period occurs at the falling edge of the ninth clock only when
Remark
(1) During address transmission/reception
(2) During data reception
(3) During data transmission
(4) Wait cancellation method
(5) Stop condition detection
WTIM
• Slave device operation:
• Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of the
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM bit.
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM bit.
The four wait cancellation methods are as follows.
• Writing data to the IICA shift register (IICA)
• Setting bit 5 (WREL) of IICA control register 0 (IICCTL0) (canceling wait)
• Setting bit 1 (STT) of IICCTL0 register (generating start condition)
• Setting bit 0 (SPT) of IICCTL0 register (generating stop condition)
When an 8-clock wait has been selected (WTIM = 0), the presence/absence of ACK generation must be
determined prior to wait cancellation.
INTIICA is generated when a stop condition is detected (only when SPIE = 1).
0
1
Note Master only.
2. If the received address does not match the contents of the slave address register (SVA) and extension code
there is a match with the address set to the slave address register (SVA).
At this point, ACK is generated regardless of the value set to the IICCTL0 register’s bit 2 (ACKE). For a slave
device that has received an extension code, INTIICA occurs at the falling edge of the eighth clock.
However, if the address does not match after restart, INTIICA is generated at the falling edge of the 9th
clock, but wait does not occur.
is not received, neither INTIICA nor a wait occurs.
The numbers in the table indicate the number of the serial clock’s clock signals. Interrupt requests and wait
control are both synchronized with the falling edge of these clock signals.
Address
9
9
Notes 1, 2
Notes 1, 2
During Slave Device Operation
Table 15-2. INTIICA Generation Timing and Wait Control
Data Reception
Notes 1 and 2 above, regardless of the WTIM bit.
WTIM bit.
Interrupt and wait timing are determined depending on the conditions described in
8
9
Note 2
Note 2
Data Transmission
8
9
Note 2
Note 2
Address
CHAPTER 15 SERIAL INTERFACE IICA
Note
Note
9
9
During Master Device Operation
Data Reception
8
9
Data Transmission
8
9
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