UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 547

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
12.4 Operation of Watchdog Timer
12.4.1 Controlling operation of watchdog timer
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
1.
2.
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5.
Cautions 1. When data is written to the watchdog timer enable register (WDTE) for the first time after reset
When the watchdog timer is used, its operation is specified by the option byte (000C0H).
• Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the
• Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H) (for details, see 12.4.2
• Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (000C0H) (for
After a reset release, the watchdog timer starts counting.
By writing “ACH” to the watchdog timer enable register (WDTE) after the watchdog timer starts counting and before
the overflow time set by the option byte, the watchdog timer is cleared and starts counting again.
After that, write the WDTE register the second time or later after a reset release during the window open period. If
the WDTE register is written during a window close period, an internal reset signal is generated.
If the overflow time expires without “ACH” written to the WDTE register, an internal reset signal is generated.
An internal reset signal is generated in the following cases.
• If a 1-bit manipulation instruction is executed on the WDTE register
• If data other than “ACH” is written to the WDTE register
counter starts operating after a reset release) (for details, see CHAPTER 25).
and CHAPTER 25).
details, see 12.4.3 and CHAPTER 25).
WDTON
0
1
2. If the watchdog timer is cleared by writing “ACH” to the WDTE register, the actual overflow time
3. The watchdog timer can be cleared immediately before the count value overflows.
release, the watchdog timer is cleared in any timing regardless of the window open time, as long
as the register is written before the overflow time, and the watchdog timer starts counting again.
may be different from the overflow time set by the option byte by up to 2/f
Counter operation disabled (counting stopped after reset)
Counter operation enabled (counting started after reset)
Watchdog Timer Counter
CHAPTER 12 WATCHDOG TIMER
IL
seconds.
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