UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 770

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(4) IICA flag register (IICF)
This register sets the operation mode of I
The IICF register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the STT clear flag
(STCF) and I
The IICRSV bit can be used to enable/disable the communication reservation function.
The STCEN bit can be used to set the initial value of the IICBSY bit.
The IICRSV and STCEN bits can be written only when the operation of I
register 0 (IICCTL0) = 0). When operation is enabled, the IICF register can be read.
Reset signal generation clears this register to 00H.
Remark
Condition for clearing (ACKD = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LREL = 1 (exit from communications)
• When the IICE bit changes from 1 to 0 (operation
• Reset
Condition for clearing (STD = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LREL = 1 (exit from communications)
• When the IICE bit changes from 1 to 0 (operation
• Reset
Condition for clearing (SPD = 0)
• At the rising edge of the address transfer byte’s first
• When the IICE bit changes from 1 to 0 (operation
• Reset
stop)
ACKD
following address transfer
stop)
clock following setting of this bit and detection of a
start condition
stop)
SPD
STD
2
0
1
0
1
0
1
C bus status flag (IICBSY) bits are read-only.
LREL:
IICE:
Acknowledge was not detected.
Acknowledge was detected.
Start condition was not detected.
Start condition was detected. This indicates that the address transfer period is in effect.
Stop condition was not detected.
Stop condition was detected. The master device’s communication is terminated and the bus is
released.
Figure 15-7. Format of IICA Status Register (IICS) (3/3)
Bit 7 of IICA control register 0 (IICCTL0)
Bit 6 of IICA control register 0 (IICCTL0)
2
C and indicates the status of the I
Detection of acknowledge (ACK)
Detection of start condition
Detection of stop condition
Condition for setting (ACKD = 1)
• After the SDA0 line is set to low level at the rising
Condition for setting (STD = 1)
• When a start condition is detected
Condition for setting (SPD = 1)
• When a stop condition is detected
edge of SCL0 line’s ninth clock
CHAPTER 15 SERIAL INTERFACE IICA
2
C is disabled (bit 7 (IICE) of IICA control
2
C bus.
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