UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 359

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(8) Operation speed mode control register (OSMC)
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
This register is used to reduce power consumption by stopping as many unnecessary clock functions as possible.
The FLPC and FSEL bits can be used to control the step-up circuit of the flash memory for high-speed operation.
If the microcontroller operates on a system clock of 10 MHz or more, set this register to 01B.
If the microcontroller operates at low speed on a system clock of 10 MHz or less, power consumption can be reduced,
because the voltage booster can be stopped by setting this register to its initial value, 00B. Furthermore, when CPU
operates with the system clock of 1 MHz, the power consumption can be further reduced by setting the FLPC bit to 1.
If the RTCLPC bit is set to 1 and real-time counter is operating, current consumption can be reduced, because the
circuit that synchronizes the clock to the peripheral functions, except the real-time counter
mode and in HALT mode while subsystem clock
The OSMC register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: F00F3H
Symbol
OSMC
Notes 1. 40-pin product of the 78K0R/KC3-L does not have real-time counter.
Note
Cautions 1. Write “1” to the FSEL bit before the following two operations.
(Cautions are given on the next page.)
RTCLPC
FLPC
RTCLPC
0
0
1
1
0
1
Figure 7-12. Format of Operation Speed Mode Control Register (OSMC)
2. 40-pin product of the 78K0R/KC3-L does not have subsystem clock.
40-pin product of the 78K0R/KC3-L does not have RTCLPC bit. Be sure to clear RTCLPC bit to 0.
7
Note
After reset: 00H
2. The CPU waits (140.5 clock (f
3. To increase f
4. To set the FSEL bit to 0, set f
5. Set FSEL = 0 to shift to STOP mode while V
Enables supply of subsystem clock to peripheral functions
(See Table 20-1 for peripheral functions whose operations are enabled.)
Stops supply of subsystem clock to peripheral functions other than real-time counter
• Changing the clock prior to dividing f
• Operating the DMA controller.
Interrupt requests issued during a wait will be suspended.
However, counting the oscillation stabilization time of f
CPU is waiting.
three or more clocks have elapsed.
Setting in STOP mode and in HALT mode while subsystem clock is selected as CPU clock
FSEL
0
1
0
1
6
0
Operates at a frequency of 10 MHz or less (default).
Operates at a frequency higher than 10 MHz.
Operates at a frequency of 1 MHz.
Setting prohibited
R/W
CLK
5
0
to 10 MHz or higher, set the FSEL bit to “1”, then change f
Note 2
is selected as CPU clock.
4
0
CLK
CLK
)) when “1” is written to the FSEL bit.
to 10 MHz or less in advance.
f
CLK
frequency selection
3
0
CLK
to a clock other than f
DD
CHAPTER 7 CLOCK GENERATOR
≤ 2.7 V.
2
0
X
can continue even while the
FLPC
1
Note 1
IH
, is stopped in STOP
.
FSEL
0
CLK
after
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