UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 329

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(6) A/D port configuration register (ADPC)
Address: F0017H
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Symbol
ADPC
This register switches the P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 pins to digital I/O of port or analog
input of A/D converter.
The ADPC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 10H.
Cautions 1. Set the channel used for A/D conversion to the input mode by using port mode registers 2 and
Remark P20/ANI0 to P27/ANI7, P150/ANI8 to P153/ANI11: 78K0R/KF3-L
ADP
C4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Other than above
ADP
7
0
C3
P20/ANI0 to P27/ANI7, P150/ANI8 to P157/ANI15: 78K0R/KG3-L
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
2. Do not set the pin set by the ADPC register as digital I/O by the analog input channel
3. P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 are set as analog inputs in the order of
4. Be sure to first set the ADCEN bit of peripheral enable register 0 (PER0) to 1 when setting up the
ADP
After reset: 10H
15 (PM2, PM15).
specification register (ADS).
P157/ANI15, …, P150/ANI8, P27/ANI7, …, P20/ANI0 by the A/D port configuration register (ADPC).
When using P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 as analog inputs, start
designing from P157/ANI15.
ADPC register. If ADCEN = 0, writing to the ADPC register is ignored and specified values are
returned to the initial values.
C2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
ADP
C1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
Figure 6-60. Format of A/D Port Configuration Register (ADPC)
6
0
ADP
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
ANI15/
P157
Setting prohibited
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
R/W
ANI14/
P156
D
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
5
0
ANI13/
P155
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
CHAPTER 6 PORT FUNCTIONS (78K0R/KF3-L, 78K0R/KG3-L)
ANI12/
P154
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
Port 15
ADPC4
ANI11/
P153
4
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
A
A
Analog input (A)/digital I/O (D) switching
ANI10/
P152
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
A
ANI9/
P151
ADPC3
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
A
3
ANI8/
P150
D
D
D
D
D
D
D
D
A
A
A
A
A
A
A
A
A
ANI7/
P27
D
D
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
ADPC2
ANI6/
P26
2
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
ANI5/
P25
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
ANI4/
P24
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
ADPC1
Port 2
1
ANI3/
P23
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
ANI2/
P22
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
A
ADPC0
ANI1/
P21
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
A
0
ANI0/
P20
D
D
D
D
D
A
D
D
D
D
D
D
D
D
D
D
D
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