UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 116
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UPD78F1001GA-HAA-AX
Manufacturer Part Number
UPD78F1001GA-HAA-AX
Description
MCU 16BIT 78K0R/KX3-L 44-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1001GA-HAA-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1001GA-HAA-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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<R>
78K0R/Kx3-L
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
3.3.1 78K0R/KF3-L
see Figure 3-1. Pin I/O Circuit List.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
P02/SO10/TxD1
P03/SI10/RxD1/SDA10
P04/SCK10/SCL10
P05/TI05/TO05
P06/TI06/TO06
P10/SCK00
P11/SI00/RxD0
P12/SO00/TxD0
P13/TxD3
P14/RxD3
P15/RTCDIV/RTCCL
P16/TI01/TO01/INTP5
P17/TI02/TO02
P20/ANI0 to P27/ANI7
P30/RTC1HZ/INTP3
P31/TI03/TO03/INTP4
P40/TOOL0
Table 3-3 shows the types of pin I/O circuits and the recommended connections of unused pins. For I/O Circuit Type,
Note P20/ANI0 to P27/ANI7 are set in the digital input port mode after release of reset.
Pin Name
Note
5-AG
5-AN
8-R
5-AN
5-AG
8-R
5-AG
8-R
11-G
8-R
I/O Circuit Type
Table 3-3. Connection of Unused Pins (1/3)
I/O
CHAPTER 3 PIN FUNCTIONS (78K0R/KF3-L, 78K0R/KG3-L)
I/O
Input:
Output: Leave open.
<When N-ch open-drain>
Set the port output latch to 0 and leave open with low level out put.
Input:
Output: Leave open.
Input:
Output: Leave open.
<When N-ch open-drain>
Set the port output latch to 0 and leave open with low level out put.
Input:
Output: Leave open.
Input:
Output: Leave open.
<When N-ch open-drain>
Set the port output latch to 0 and leave open with low level out put.
Input:
Output: Leave open.
Input:
Output: Leave open.
Input:
Output: Leave open.
Input:
Output: Leave open.
<When on-chip debugging is enabled>
Pull this pin up (pulling it down is prohibited).
<When on-chip debugging is disabled>
Input:
Output: Leave open.
Independently connect to EV
Independently connect to EV
Independently connect to EV
Independently connect to EV
Independently connect to EV
Independently connect to EV
Independently connect to EV
Independently connect to AV
Independently connect to EV
Independently connect to EV
Recommended Connection of Unused Pins
DD0
DD0
DD0
DD0
DD0
DD0
DD0
REF
DD0
DD0
or EV
or EV
or EV
or EV
or EV
or EV
or EV
or AV
or EV
or EV
SS0
SS0
SS0
SS0
SS0
SS0
SS0
SS
SS0
SS0
via a resistor.
via a resistor.
via a resistor.
via a resistor.
via a resistor.
via a resistor.
via a resistor.
via a resistor.
via a resistor.
via a resistor.
116
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