UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 910

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(1) Oscillation stabilization time counter status register (OSTC)
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Note
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter.
The X1 clock oscillation stabilization time can be checked in the following case.
The OSTC register can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, WDT, and executing an illegal instruction), the STOP
instruction and MSTOP bit (bit 7 of clock operation status control register (CSC)) = 1 clear this register to 00H.
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or subsystem clock
• If the STOP mode is entered and then released while the internal high-speed oscillation clock is being used as
Address: FFFA2H
Symbol
used as the CPU clock.
the CPU clock with the X1 clock oscillating.
OSTC
The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
Figure 20-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Remark f
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from the MOST8
MOST
MOST
7
8
8
0
1
1
1
1
1
1
1
1
MOST
MOST
After reset: 00H
2. The oscillation stabilization time counter counts up to the oscillation
3. The X1 clock oscillation stabilization wait time does not include the time until
X
: X1 clock oscillation frequency
6
9
9
0
0
1
1
1
1
1
1
1
bit and remain 1.
stabilization time set by the oscillation stabilization time select register (OSTS).
If the STOP mode is entered and then released while the internal high-speed
oscillation clock is being used as the CPU clock, set the oscillation stabilization
time as follows.
Note, therefore, that only the status up to the oscillation stabilization time set
by the OSTS register is set to the OSTC register after STOP mode is released.
clock oscillation starts (“a” below).
MOST
MOST
•
10
10
5
0
0
0
1
1
1
1
1
1
stabilization time set by OSTS register
Desired OSTC register oscillation stabilization time ≤ Oscillation
X1 pin voltage
waveform
MOST
MOST
11
11
4
0
0
0
0
1
1
1
1
1
R
MOST
MOST
13
13
STOP mode release
3
0
0
0
0
0
1
1
1
1
MOST
MOST
15
15
2
0
0
0
0
0
0
1
1
1
a
MOST
MOST
17
17
1
0
0
0
0
0
0
0
1
1
MOST
MOST
18
18
0
0
0
0
0
0
0
0
0
1
CHAPTER 20 STANDBY FUNCTION
2
2
2
2
2
2
2
2
2
8
8
9
10
11
13
15
17
18
/f
/f
/f
/f
/f
/f
/f
/f
/f
Oscillation stabilization time status
X
X
X
X
X
X
X
X
X
max. 25.6
min. 25.6
min. 51.2
min. 102.4
min. 204.8
min. 819.2
min. 3.27 ms min.
min. 13.11 ms min. 6.55 ms min.
min. 26.21 ms min. 13.11 ms min.
f
X
= 10 MHz
μ
μ
μ
s max.
s min.
s min.
μ
μ
μ
s min. 51.2
s min. 102.4
s min. 409.6
12.8
25.6
1.64 ms min.
12.8
f
X
= 20 MHz
μ
μ
μ
μ
s max.
s min.
s min.
s min.
μ
μ
s min.
s min.
Note
is being
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