UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 468

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
8.8 Simultaneous Channel Operation Function of Timer Array Unit
8.8.1 Operation as one-shot pulse output function
to the TImn pin.
master channel starts operating upon start trigger detection and loads the value of timer data register mn (TDRmn).
clock. When TCRmn = 0000H, it outputs INTTMmn and stops counting until the next start trigger is detected.
channel starts operation using INTTMmn of the master channel as a start trigger, and loads the value of the TDRmp
register. The TCRmp register counts down from the value of The TDRmp register it has loaded, in synchronization with
the count value. When count value = 0000H, it outputs INTTMmp and stops counting until the next start trigger (INTTMmn
of the master channel) is detected. The output level of TOmp becomes active one count clock after generation of
INTTMmn from the master channel, and inactive when TCRmp = 0000H.
start trigger.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
By using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal input
The delay time and pulse width can be calculated by the following expressions.
The master channel operates in the one-count mode and counts the delays. Timer/counter register mn (TCRmn) of the
The TCRmn register counts down from the value of the TDRmn register it has loaded, in synchronization with the count
The slave channel operates in the one-count mode and counts the pulse width. The TCRmp register of the slave
Instead of using the TImn pin input, a one-shot pulse can also be output using the software operation (TSmn = 1) as a
Caution The timing of loading of timer data register mn (TDRmn) of the master channel is different from that of
Remark
Note
Delay time = {Set value of TDRmn (master) + 2} × Count clock period
Pulse width = {Set value of TDRmp (slave)} × Count clock period
the TDRmp register of the slave channel. If the TDRmn and TDRmp registers are rewritten during
operation, therefore, an illegal waveform is output. Rewrite the TDRmn register after INTTMmn is
generated and the TDRmp register after INTTMmp is generated.
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6)
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04, 06
78K0R/KF3-L, 78K0R/KG3-L:
p: Slave channel number
When m = 0: n < p ≤ 7
When m = 1: n < p ≤ 3
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be used as the
slave channel.
Note
mn = 00, 02, 04, 06, 10, 12
CHAPTER 8 TIMER ARRAY UNIT
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