UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 283

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UPD78F1000GB-GAF-AX

Manufacturer Part Number
UPD78F1000GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet

Specifications of UPD78F1000GB-GAF-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1000GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
78K0R/Kx3-L
Note
mode register 5 (PM5). When the P50 to P57 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 5 (PU5).
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
6.2.6 Port 5 (
P50/INTP1
P51/INTP2
P52/TO00
P53/TI00
P54/TI07/TO07
P55/PCLBUZ1/INTP7
P56
P57
Port 5 is an I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port
This port can also be used for external interrupt request input, timer I/O, and clock/buzzer output.
Reset signal generation sets port 5 to input mode.
Figures 6-23 to 6-26 show block diagrams of port 5.
Cautions 1. To use P52/TO00 or P54/TI07/TO07 as a general-purpose port, set bits 0 and 7 (TO00, TO07) of
The following pins are shared in the 78K0R/KG3-L.
• P46/INTP1
• P47/INTP2
• P01/TO00
• P00/TI00
• P145/TI07/TO07
• P141/PCLBUZ1/INTP7
2. To use P55/PCLBUZ1/INTP7 as a general-purpose port, set bit 7 of clock output select register 1
μ
PD78F1010, 78F1011, 78F1012, 78F1013, 78F1014)
timer output register 0 (TO0) and bits 0 and 7 (TOE00, TOE07) of timer output enable register 0
(TOE0) to “0”, which is the same as their default status setting.
(CKS1) to “0”, which is the same as their default status settings.
(
μ PD78F101y: y = 0 to 2)
78K0R/KF3-L
CHAPTER 6 PORT FUNCTIONS (78K0R/KF3-L, 78K0R/KG3-L)
(
μ PD78F101y: y = 3, 4)
78K0R/KG3-L
P50
P54
P51
P52
P53
P55
Note
Note
Note
Note
Note
Note
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