UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 908

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
20.1 Standby Function and Configuration
20.1.1 Standby function
(1) HALT mode
(2) STOP mode
are held. The I/O port output latches and output buffer statuses are also held.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The standby function reduces the operating current of the system, and the following two modes are available.
Note
In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set
Cautions 1. The STOP mode can be used only when the CPU is operating on the main system clock. The
Remark n = 0, 1
HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the high-
speed system clock oscillator, internal high-speed oscillator, 20 MHz internal high-speed oscillator, or subsystem
clock oscillator
operating current is not decreased as much as in the STOP mode, but the HALT mode is effective for restarting
operation immediately upon interrupt request generation and carrying out intermittent operations frequently.
STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator and
internal high-speed oscillator stop, stopping the whole system, thereby considerably reducing the CPU operating
current.
Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.
However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is released
when the X1 clock is selected, select the HALT mode if it is necessary to start processing immediately upon interrupt
request generation.
The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation operating
3. The following sequence is recommended for operating current reduction of the A/D converter
4. The following sequence is recommended for operating current reduction of the comparator when
5. The following sequence is recommended for operating current reduction of the programmable
STOP mode cannot be set while the CPU operates with the subsystem clock. The HALT mode
can be used when the CPU is operating on either the main system clock or the subsystem clock.
with main system clock before executing STOP instruction.
when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter
mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the STOP
instruction.
the standby function is used: First clear bit 7 (CnEN) of the comparator n control register (CnCTL)
and bit 7 (CnVRE) of the comparator n internal reference voltage selection register to 0 to stop
the comparator operation, and then execute the STOP instruction.
gain amplifier when the standby function is used: First clear bit 7 (OAEN) of the programmable
gain amplifier control register (OAM) to 0 to stop the programmable gain amplifier operation, and
then execute the STOP instruction.
Note
is operating before the HALT mode is set, oscillation of each clock continues. In this mode, the
CHAPTER 20 STANDBY FUNCTION
CHAPTER 20 STANDBY FUNCTION
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