UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 379

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(4) CPU operating with 20 MHz internal high-speed oscillation clock (J) after reset release (A)
(5) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(A) → (B) → (J)
Status Transition
Status Transition
(B) → (C)
(X1 clock: 2 MHz ≤ fX ≤ 10 MHz)
(B) → (C)
(X1 clock: 10 MHz < fX ≤ 20 MHz)
(B) → (C)
(external main clock)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
Note
Notes 1. The clock operation mode control register (CMC) can be changed only once after reset release. This
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
Remarks 1. ×: don’t care
(Setting sequence of SFR registers)
Check that V
Setting Flag of SFR Register
2. Set the oscillation stabilization time as follows.
3. FSEL = 1 when f
(Setting sequence of SFR registers)
CHAPTER 30 ELECTRICAL SPECIFICATIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L) or
CHAPTER 31 ELECTRICAL SPECIFICATIONS (78K0R/KF3-L, 78K0R/KG3-L)).
2. (A) to (K) in Table 7-4 correspond to (A) to (K) in Figure 7-19.
setting is not necessary if it has already been set.
• Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time ≤
If a divided clock is selected and f
Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
Setting Flag of SFR Register
Table 7-4. CPU Clock Transition and SFR Register Setting Examples (2/6)
DD
≥ 2.7 V and set DSCON = 1.
CLK
> 10 MHz
Unnecessary if these registers
EXCLK
0
0
1
CMC Register
are already set
DSCCTL Register
OSCSEL
CLK
1
1
1
≤ 10 MHz, use with FSEL = 0 is possible even if f
DSCON
1
Note 1
AMPH
×
0
1
Note
Unnecessary if the CPU is operating with
Register
Note 2
Note 2
Note 2
OSTS
Waiting for Oscillation
the high-speed system clock
Stabilization
Necessary
(100
Register
MSTOP
CHAPTER 7 CLOCK GENERATOR
CSC
0
0
0
μ
s)
Register
OSMC
FSEL
1
0/1
Note 3
0
Must not
Register
checked
checked
checked
DSCCTL Register
Must be
Must be
OSTC
be
SELDSC
X
> 10 MHz.
1
Register
MCM0
CKC
1
1
1
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