UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 475

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
8.8.2 Operation as PWM function
register m (TSm) is set to 1, an interrupt (INTTMmn) is output, the value set to timer data register mn (TDRmn) is loaded
to timer/counter register mn (TCRmn), and the counter counts down in synchronization with the count clock. When the
counter reaches 0000H, INTTMmn is output, the value of the TDRmn register is loaded again to the TCRmn register, and
the counter counts down. This operation is repeated until the channel stop trigger bit (TTmn) of timer channel stop
register m (TTm) is set to 1.
PWM output (TOmp) cycle.
TCRmp register loads the value of the TDRmp register and the counter counts down to 0000H. When the counter
reaches 0000H, it outputs INTTMmp and waits until the next start trigger (INTTMmn from the master channel) is generated.
PWM output (TOmp) duty.
inactive level when the TCRmp register of the slave channel becomes 0000H.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Two channels can be used as a set to generate a pulse of any period and duty factor.
The period and duty factor of the output pulse can be calculated by the following expressions.
The master channel operates in the interval timer mode. If the channel start trigger bit (TSmn) of timer channel start
If two channels are used to output a PWM waveform, the period until the master channel counts down to 0000H is the
The slave channel operates in one-count mode. By using INTTMmn from the master channel as a start trigger, the
If two channels are used to output a PWM waveform, the period until the slave channel counts down to 0000H is the
PWM output (TOmp) goes to the active level one clock after the master channel generates INTTMmn and goes to the
Caution To rewrite both timer data register mn (TDRmn) of the master channel and the TDRmp register of the
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6)
Remark
Pulse period = {Set value of TDRmn (master) + 1} × Count clock period
Duty factor [%] = {Set value of TDRmp (slave)}/{Set value of TDRmn (master) + 1} × 100
0% output:
100% output: Set value of TDRmp (slave) ≥ {Set value of TDRmn (master) + 1}
78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L: mn = 00, 02, 04, 06
78K0R/KF3-L, 78K0R/KG3-L:
p: Slave channel number
When m = 0: n < p ≤ 7
When m = 1: n < p ≤ 3
Note
slave channel, a write access is necessary two times. The timing at which the values of the TDRmn
and TDRmp registers are loaded to the TCRmn and TCRmp registers is upon occurrence of INTTMmn
of the master channel. Thus, when rewriting is performed split before and after occurrence of
INTTMmn of the master channel, the TOmp pin cannot output the expected waveform. To rewrite both
the TDRmn register of the master and the TDRmp register of the slave, therefore, be sure to rewrite
both the registers immediately after INTTMmn is generated from the master channel.
The duty factor exceeds 100% if the set value of TDRmp (slave) > (set value of TDRmn (master) + 1), it
summarizes to 100% output.
Since there is no function of timer I/O, the channel 1 in the 78K0R/KC3-L (40-pin) can not be used as
the slave channel.
Set value of TDRmp (slave) = 0000H
Note
mn = 00, 02, 04, 06, 10, 12
CHAPTER 8 TIMER ARRAY UNIT
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