UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 796

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
15.5.15 Cautions
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(1) When STCEN = 0
(2) When STCEN = 1
(3) If other I
(4) Setting the STT and SPT bits (bits 1 and 0 of the IICCTL0 register) again after they are set and before they are
(5) When transmission is reserved, set the SPIE bit (bit 4 of the IICTL0 register) to 1 so that an interrupt request is
Immediately after I
regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to a
master device communication mode, first generate a stop condition to release the bus, then perform master device
communication.
When using multiple masters, it is not possible to perform master device communication when the bus has not
been released (when a stop condition has not been detected).
Use the following sequence for generating a stop condition.
<1> Set IICA control register 1 (IICCTL1).
<2> Set bit 7 (IICE) of IICA control register 0 (IICCTL0) to 1.
<3> Set bit 0 (SPT) of the IICCTL0 register to 1.
Immediately after I
regardless of the actual bus status. To generate the first start condition (STT = 1), it is necessary to confirm that
the bus has been released, so as to not disturb other communications.
If I
low and the SCL0 pin is high, the macro of I
condition). If the value on the bus at this time can be recognized as an extension code, ACK is returned, but this
interferes with other I
<1> Clear bit 4 (SPIE) of the IICCTL0 register to 0 to disable generation of an interrupt request signal (INTIICA)
<2> Set bit 7 (IICE) of the IICCTL0 register to 1 to enable the operation of I
<3> Wait for detection of the start condition.
<4> Set bit 6 (LREL) of the IICCTL0 register to 1 before ACK is returned (4 to 80 clocks after setting the IICE bit to
cleared to 0 is prohibited.
generated when the stop condition is detected. Transfer is started when communication data is written to the IICA
shift register (IICA) after the interrupt request is generated. Unless the interrupt is generated when the stop
condition is detected, the device stops in the wait state because the interrupt request is not generated when
communication is started. However, it is not necessary to set the SPIE bit to 1 when the MSTS bit (bit 7 of the IICA
status register (IICS)) is detected by software.
2
C operation is enabled and the device participates in communication already in progress when the SDA0 pin is
when the stop condition is detected.
1), to forcibly disable detection.
2
C communications are already in progress
2
C operation is enabled (IICE = 1), the bus communication status (IICBSY = 1) is recognized
2
C operation is enabled (IICE = 1), the bus released status (IICBSY = 0) is recognized
2
C communications. To avoid this, start I
2
C recognizes that the SDA0 pin has gone low (detects a start
2
C in the following sequence.
CHAPTER 15 SERIAL INTERFACE IICA
2
C.
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