UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 871

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Maskable
Interrupt
Type
Notes 1.
4.
2.
3.
Default
Priority
Note 1
10
11
12
13
14
15
16
17
18
19
0
1
2
3
4
5
6
7
8
9
The default priority determines the sequence of interrupts if two or more maskable interrupts request occur
simultaneously. Zero indicates the highest priority and 47 indicate the lowest priority.
Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 18-1.
When bit 7 (WDTINT) of the option byte (000C0H) is set to 1.
When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is cleared to 0.
INTWDTI
INTLVI
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTST3
INTCMP0
INTSR3
INTCMP1
INTSRE3
INTDMA0
INTDMA1
INTST0/
INTCSI00
INTSR0/
INTCSI01
INTSRE0
INTST1
/INTCSI10
/INTIIC10
INTSR1
INTSRE1
INTIICA
Name
Interrupt Source
(75% of overflow time)
UART3 reception transfer end
UART3 reception
communication error occurrence
UART1 transmission transfer end
or buffer empty interrupt/CSI10
transfer end or buffer empty
interrupt/IIC10 transfer end
UART1 reception transfer end
UART1 reception
communication error occurrence
Watchdog timer interval
Low-voltage detection
Pin input edge detection
UART3 transmission transfer
end or buffer empty interrupt
CMP0 detection
CMP1 detection
End of DMA0 transfer
End of DMA1 transfer
UART0 transmission transfer
end or buffer empty
interrupt/CSI00 transfer end
or buffer empty interrupt
UART0 reception transfer
end/CSI01 transfer end or
buffer empty interrupt
UART0 reception
communication error occurrence
End of IICA communication
Table 18-1. Interrupt Source List (1/3)
Trigger
Note 4
Note 3
Internal
External
Internal
External
Internal/
Address
CHAPTER 18 INTERRUPT FUNCTIONS
Vector
000AH
000CH
000EH
001AH
001CH
001EH
002AH
0004H
0006H
0008H
0010H
0012H
0014H
0016H
0018H
0020H
0022H
0024H
0026H
0028H
Table
Configuration
Type
Basic
(A)
(B)
(A)
Note 2
√
√
√
√
√
√
√
√
−
√
−
√
−
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
√
√
−
√
−
√
−
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
√
√
−
√
−
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
−
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
−
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
−
√
√
√
√
√
√
√
√
√
√
871
√
√
√
√
√
√
√
√
√
−
√
−
√
√
√
√
√
√
√
√
√
√