UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 858
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UPD78F1000GB-GAF-AX
Manufacturer Part Number
UPD78F1000GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1000GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1000GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
17.4.2 Transfer mode
control register n (DMCn).
data resulting from A/D conversion can be consecutively transferred, and port data can be scanned at fixed time intervals
by using a timer.
17.4.3 Termination of DMA transfer
(INTDMAn) is generated and transfer is terminated.
address register n (DRAn) hold the value when transfer is terminated.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
The following four modes can be selected for DMA transfer by using bits 6 and 5 (DRSn and DSn) of DMA mode
By using these transfer modes, up to 1024 bytes of data can be consecutively transferred by using the serial interface,
When DBCn = 00H and DMA transfer is completed, the DSTn bit is automatically cleared to 0. An interrupt request
When the DSTn bit is cleared to 0 to forcibly terminate DMA transfer, DMA byte count register n (DBCn) and DMA RAM
The interrupt request (INTDMAn) is not generated if transfer is forcibly terminated.
Remark
DRSn
0
0
1
1
DSn
n: DMA channel number (n = 0, 1)
0
1
0
1
Transfer from SFR of 1-byte data (fixed address) to RAM (address is incremented by +1)
Transfer from SFR of 2-byte data (fixed address) to RAM (address is incremented by +2)
Transfer from RAM of 1-byte data (address is incremented by +1) to SFR (fixed address)
Transfer from RAM of 2-byte data (address is incremented by +2) to SFR (fixed address)
DMA Transfer Mode
CHAPTER 17 DMA CONTROLLER
858
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