UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 1157

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Previous
version
(U19291E)
2nd edition
Edition
Change of description during operation in Figure 6-54 Operation Procedure When
Input Signal High-/Low-Level Width Measurement Function Is Used
Change of description during operation in Figure 6-59 Operation Procedure When
PWM Function Is Used
Change of description during operation in Figure 6-64 Operation Procedure of One-
Shot Pulse Output Function
Change of description during operation in Figure 6-69 Operation Procedure When
Multiple PWM Output Function Is Used
Change of description of the CT2 to CT1 bits in Figure 7-3 Format of Real-Time
Counter Control Register 0 (RTCC0)
Change of description of the WALE bit in Figure 7-4 Format of Real-Time Counter
Control Register 1 (RTCC1)
Addition of Caution 3 to Figure 7-5 Format of Real-Time Counter Control Register
2 (RTCC2)
Change of description in 7.3 (7) Minute count register (MIN), (8) Hour count
register (HOUR), (9) Day count register (DAY), (11) Month count register
(MONTH), and (12) Year count register (YEAR)
Addition of description to 7.3 (13) Watch error correction register (SUBCUD)
Addition of Caution 3 to Figure 8-3. Format of Programmable Gain Amplifier
Control Register (OAM)
Addition of Caution 5 to Figure 8-4. Format of Comparator n Control Register
(CnCTL)
Addition of Caution 4 to Figure 8-5. Format of Comparator n Internal Reference
Voltage Selection Register (CnRVM)
Change of Caution 2 in Figure 9-2. Format of Clock Output Select Register n
(CKSn)
Change of Remark 1 in 9.4.1 Operation as output pin
Change of Figure 9-4. Remote Control Output Application Example
Addition of Caution 3 to Figure 13-3. Format of IICA Shift Register (IICA)
Change of Figure 13-6. Format of IICA Control Register 0 (IICCTL0)
Addition of description to the WUP bit in Figure 13-9. Format of IICA Control
Register 1 (IICCTL1)
Addition of 13.4.2 Setting transfer clock by using IICWL and IICWH registers
Deletion of description in Figure 13-23. Flow When Setting WUP = 0 upon
Address Match (Including Extension Code Reception)
Deletion of descriptions in 13.5.13 Wakeup function
Change of Figure 13-24. When Operating as Master Device after Releasing
STOP Mode other than by INTIICA
Deletion of Figure 13-25. When Operating as Slave Device after Releasing STOP
Mode other than by INTIICA (When Not Required to Operate as Master Device)
Change of description in 11.6 (1) Operating current in STOP mode
Change of (b) When receiving last data in Figure 12-95. Timing Chart of Data
Reception
Description
APPENDIX B REVISION HISTORY
CHAPTER 12 SERIAL
ARRAY UNIT
CHAPTER 13 SERIAL
INTERFACE IICA
CHAPTER 6 TIMER
ARRAY UNIT
CHAPTER 7 REAL-
TIME COUNTER
CHAPTER 8
COMPARATORS/PROG
RAMMABLE GAIN
AMPLIFIERS
CHAPTER 9 CLOCK
OUTPUT/BUZZER
OUTPUT
CONTROLLER
CHAPTER 11 A/D
CONVERTER
Chapter
(2/7)
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