UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 288

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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78K0R/Kx3-L
6.2.7 Port 5 (
Note
mode register 5 (PM5). When the P50 to P57 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 5 (PU5).
clock/buzzer output.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
P50/SCK40/INTP1
P51/SI40/RxD4/INTP2
P52/SO40/TO00/TxD4
P53/SCK41/TI00
P54/SI41/TI07/TO07
P55/PCLBUZ1/SO41/
INTP7
P56
P57
Port 5 is an I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port
This port can also be used for serial interface data I/O, clock I/O, external interrupt request input, timer I/O, and
Reset signal generation sets port 5 to input mode.
Figures 6-27 to 6-32 show block diagrams of port 5.
Cautions 1. To use P52/SO40/TO00/TxD4(P52/SO40/TO00, in case of KG3-L) or P54/SI41/TI07/TO07(P54/SI41,
The following pins are shared in the 78K0R/KG3-L.
• P46/INTP1
• P47/INTP2
• P01/TO00
• P00/TI00
• P145/TI07/TO07
• P141/PCLBUZ1/INTP7
2. To use P55/PCLBUZ1/SO41/INTP7(P55/SO41, in case of KG3-L) as a general-purpose port, set bit
3. To
μ
PD78F1027, 78F1028, 78F1029, 78F1030)
in case of KG3-L) as a general-purpose port, set bits 0 and 7 (TO00, TO07) of timer output register
0 (TO0) and bits 0 and 7 (TOE00, TOE07) of timer output enable register 0 (TOE0) to “0”, which is
the same as their default status setting.
7 of clock output select register 1 (CKS1) to “0”, which is the same as their default status settings.
P54/SI41/TI07/TO07, and P55/PCLBUZ1/SO41/INTP7 as a general-purpose port, note the serial
array unit setting.
settings and pins (Channel 0 of unit 2: CSI40, UART4 transmission) (
78F1029, 78F1030 only) and Table 14-18.
(Channel 1 of unit 2: CSI41, UART4 reception) (
use
P50/SCK40/INTP1,
(
μ
PD78F10xx: xx = 27, 28)
78K0R/KF3-L
For details, refer to Table 1 Table 14-17.
√
−
√
√
√
√
√
−
CHAPTER 6 PORT FUNCTIONS (78K0R/KF3-L, 78K0R/KG3-L)
P51/SI40/RxD4/INTP2,
(
μ
Relationship between register settings and pins
μ
PD78F10xx: xx = 29, 30)
PD78F1027, 78F1028, 78F1029, 78F1030 only).
P52/SO40/TxD4
P51/SI40/RxD4
P50/SCK40
P53/SCK41
78K0R/KG3-L
P55/SO41
P54/SI41
√
√
P52/SO40/TO00/TxD4,
Note
Note
Note
Note
Note
Note
Relationship between register
μ
PD78F1027, 78F1028,
P53/SCK41/TI00,
288