UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 443

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UPD78F1000GB-GAF-AX

Manufacturer Part Number
UPD78F1000GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet

Specifications of UPD78F1000GB-GAF-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1000GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
78K0R/Kx3-L
8.5.5 Timer Interrupt and TOmn Pin Output at Operation Start
generate a timer interrupt at count start.
operation.
change either. After counting one cycle, INTTMmn is output and TOmn performs a toggle operation.
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
In the interval timer mode or capture mode, the MDmn0 bit in timer mode register mn (TMRmn) sets whether or not to
When MDmn0 is set to 1, the count operation start timing can be known by the timer interrupt (INTTMmn) generation.
In the other modes, neither timer interrupt at count operation start nor TOmn output is controlled.
Figures 8-37 and 8-38 show operation examples when the interval timer mode (TOEmn = 1, TOMmn = 0) is set.
When MDmn0 is set to 1, a timer interrupt (INTTMmn) is output at count operation start, and TOmn performs a toggle
When MDmn0 is set to 0, a timer interrupt (INTTMmn) is not output at count operation start, and TOmn does not
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
Caution While timer output is enabled (TOEmn = 1), even if the output by timer interrupt of each timer
78K0R/KF3-L, 78K0R/KG3-L:
(INTTMmn) contends with writing to the TOmn bit, output is normally done to the TOmn pin.
However, in case of the timer output pin (TOmn), mn changes as below.
78K0R/KC3-L (40-pin):
78K0R/KC3-L (44-pin, 48-pin):
78K0R/KD3-L, 78K0R/KE3-L:
However, in case of the timer output pin (TOmn), mn changes as below.
78K0R/KC3-L (40-pin):
78K0R/KC3-L (44-pin, 48-pin):
78K0R/KD3-L, 78K0R/KE3-L:
78K0R/KF3-L, 78K0R/KG3-L:
INTTMmn
INTTMmn
TCRmn
TCRmn
TOmn
TOmn
TEmn
TEmn
Figure 8-38. When MDmn0 is set to 1
Figure 8-39. When MDmn0 is set to 0
Count operation start
Count operation start
mn = 02 to 07
mn = 00 to 07
mn = 00 to 07
mn = 00 to 07, 10 to 13
mn = 02 to 07
mn = 00 to 07
mn = 00 to 07
mn = 00 to 07, 10 to 13
CHAPTER 8 TIMER ARRAY UNIT
443

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