UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 767
UPD78F1000GB-GAF-AX
Manufacturer Part Number
UPD78F1000GB-GAF-AX
Description
MCU 16BIT 78K0R/KX3-L 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3-Lr
Datasheet
1.UPD78F1000GB-GAF-AX.pdf
(1171 pages)
Specifications of UPD78F1000GB-GAF-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1000GB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Caution When bit 3 (TRC) of the IICA status register (IICS) is set to 1 (transmission status), bit 5
Cautions concerning set timing
• For master reception:
• For master transmission: A stop condition cannot be generated normally during the acknowledge period.
• Cannot be set to 1 at the same time as start condition trigger (STT).
• The SPT bit can be set to 1 only when in master mode.
• When the WTIM bit has been cleared to 0, if the SPT bit is set to 1 during the wait period that follows output of eight
• Setting the SPT bit to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (SPT = 0)
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• Cleared by LREL = 1 (exit from communications)
• When IICE = 0 (operation stop)
• Reset
Remark
clocks, note that a stop condition will be generated during the high-level period of the ninth clock. The WTIM bit
should be changed from 0 to 1 during the wait period following the output of eight clocks, and the SPT bit should be
set to 1 during the wait period that follows the output of the ninth clock.
SPT
0
1
(WREL) of IICA control register 0 (IICCTL0) is set to 1 during the ninth clock and wait is
canceled, after which the TRC bit is cleared (reception status) and the SDA0 line is set to
high impedance. Release the wait performed while the TRC bit is 1 (transmission status) by
writing to the IICA shift register.
Bit 0 (SPT) becomes 0 when it is read after data setting.
Stop condition is not generated.
Stop condition is generated (termination of master device’s transfer).
Figure 15-6. Format of IICA Control Register 0 (IICCTL0) (4/4)
Cannot be set to 1 during transfer.
Can be set to 1 only in the waiting period when the ACKE bit has been cleared to 0 and
slave has been notified of final reception.
Therefore, set it during the wait period that follows output of the ninth clock.
Stop condition trigger
Condition for setting (SPT = 1)
• Set by instruction
CHAPTER 15 SERIAL INTERFACE IICA
767
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