UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 594

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
Address: F0126H, F0127H (SPS0), F0166H, F0167H (SPS1)
Symbol
SPSm
Notes 1. When changing the clock selected for f
Cautions 1. Be sure to clear bits 15 to 8 to “0”.
Remarks 1. f
F0216H, F0217H (SPS2)
2.
3.
PRS
mk3
15
0
0
0
0
0
0
0
0
1
1
1
1
1
0
so after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array
unit (SAU). When selecting INTTM02 for the operation clock, also stop the timer array unit 0 (timer
channel stop register 0 (TT0) = 00FFH).
2. After setting bit 2 (SAU0EN) of the PER0 register, bit 3 (SAU1EN) of the PER0 register, and bit
(Remarks 2 and 3 are listed on the next page.)
SAU0 can be operated at a fixed division ratio of the subsystem clock, regardless of the f
(main system clock, sub system clock), by operating the interval timer for which f
selected as the count clock (setting the TIS02 bit of timer input select register 0 (TIS0) to 1) and
selecting INTTM02 by using the SPS0 register in channel 2 of TAU0. When changing f
SAU0 and TAU0 must be stopped as described in Note 1 above.
The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
Other than above
PRS
mk2
0 (SAU2EN) of the PER1 register to 1, be sure to set serial clock select register m (SPSm) after
4 or more f
f
14
CLK
SUB
0
0
0
0
1
1
1
1
0
0
0
0
1
0
: CPU/peripheral hardware clock frequency
: Subsystem clock frequency
Figure 14-6. Format of Serial Clock Select Register m (SPSm) (1/2)
PRS
mk1
13
0
0
1
1
0
0
1
1
0
0
1
1
1
0
CLK
PRS
mk0
12
0
1
0
1
0
1
0
1
0
1
0
1
1
0
clocks have elapsed.
f
f
f
f
f
f
f
f
f
f
f
f
INTTM02 if m = 0
Setting prohibited
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
11
0
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
2
3
4
5
6
7
8
9
10
11
10
0
9
0
CLK
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.3 kHz
15.6 kHz
7.81 kHz
3.91 kHz
1.95 kHz
977 Hz
Note 2
f
CLK
After reset: 0000H
(by changing the system clock control register (CKC) value), do
, setting prohibited if m = 1
= 2 MHz
8
0
Section of operation clock (CKmk)
PRS
m13
7
5 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.77 kHz
4.88 kHz
2.44 kHz
f
PRS
m12
CLK
6
= 5 MHz
R/W
CHAPTER 14 SERIAL ARRAY UNIT
PRS
m11
5
PRS
m10
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 kHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
9.77 kHz
4.88 kHz
4
f
CLK
= 10 MHz
Note 1
PRS
m03
3
PRS
m02
2
5 MHz
313 kHz
156 kHz
78.1 kHz
39.1 kHz
19.5 kHz
20 MHz
10 MHz
2.5 MHz
1.25 MHz
625 kHz
9.77 kHz
SUB
f
CLK
PRS
m01
/4
= 20 MHz
1
Note 3
CLK
CLK
, however,
frequency
PRS
has been
m00
0
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