UPD78F1000GB-GAF-AX Renesas Electronics America, UPD78F1000GB-GAF-AX Datasheet - Page 211

• Manufacturer Part Number: UPD78F1000GB-GAF-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1000GB-GAF-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
5.2.8 Port 7
Remark √: Mounted
mode register 7 (PM7). When the P70 to P77 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 7 (PU7).
units using port input mode register 7 (PIM7).
using port output mode register 7 (POM7).
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
P70/KR0/SO01/
INTP4
P71/KR1/SI01/
INTP5
P72/KR2/
SCK01/INTP6
P73/KR3/SO00/
TxD0
P74/KR4/SI00/
RxD0
P75/KR5/SCK00
P76/KR6
P77/KR7
Port 7 is an I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port
Input to the P71, P72, P74, and P75 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit
Output from the P70, P72, P73, and P75 pins can be specified as N-ch open-drain output (V
This port can also be used for key return input, serial interface data I/O, clock I/O, and external interrupt request input.
Reset signal generation sets port 7 to input mode.
Figures 5-15 to 5-18 show block diagrams of port 7.
Caution To use P70/KR0/SO01/INTP4, P71/KR1/SI01/INTP5, P72/KR2/SCK01/INTP6, P73/KR3/SO00/TxD0,
P74/KR4/SI00/RxD0, P75/KR5/SCK00 as a general-purpose port, note the serial array unit setting. For
details, refer to Table 14-5 Relationship Between Register Settings and Pins (Channel 0: CSI00,
UART0 Transmission) and Table 14-6 Relationship Between Register Settings and Pins (Channel 1:
CSI01, UART0 Reception).
(
μ PD78F100y: y = 0 to 3)
40-pin
78K0R/KC3-L
CHAPTER 5 PORT FUNCTIONS (78K0R/KC3-L, 78K0R/KD3-L, 78K0R/KE3-L)
√
√
√
√
√
√
−
−
44-pin
(
μ PD78F100y: y = 1 to 3)
78K0R/KC3-L (48-pin)
√
√
√
√
√
√
−
−
(
μ PD78F100y: y = 4 to 6)
78K0R/KD3-L
√
√
√
√
√
√
√
√
(
μ PD78F100y: y = 7 to 9)
DD
tolerance) in 1-bit units
78K0R/KE3-L
√
√
√
√
√
√
√
√
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