M306N4FGTFP#U0 Renesas Electronics America, M306N4FGTFP#U0 Datasheet - Page 68

• Manufacturer Part Number: M306N4FGTFP#U0
• Description: MCU 5V 256K T-TEMP PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP#U0

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 7.4 Example in which Wait State was Inserted into Read Cycle by RDY Signal
7.2.6 RDY Signal
This signal is provided for accessing external devices which need to be accessed at low speed. If input on
the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in
the bus cycle. While in a wait state, the following signals retain the state in which they were when the RDY
signal was acknowledged.
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA
Then, when the input on the RDY pin is detected high at the falling edge of BCLK, the remaining bus cycle
is executed. Figure 7.4 shows an Example in which Wait State was Inserted into Read Cycle by RDY
Signal. To use the RDY signal, set the corresponding bit (bits CS3W to CS0W) in the CSR register to 0
(with wait state). When not using the RDY signal, the RDY pin must be pulled-up.
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Apr 14, 2006
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In an instance of multiplexed bus
In an instance of separate bus
tsu(RDY-BCLK): RDY input setup time
Shown above is the case where bits CSEi1W to CSEi0W (i = 0 to 3) in the CSE register are
00b (one wait state).
RD
RDY
RD
RDY
BCLK
CSi
(i=0 to 3)
BCLK
CSi
(i=0 to 3)
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: Wait using RDY signal
: Wait using software
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Accept timing of RDY signal
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tsu(RDY - BCLK)
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Accept timing of RDY signal
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tsu(RDY - BCLK)
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7. Bus