M306N4FGTFP#U0 Renesas Electronics America, M306N4FGTFP#U0 Datasheet - Page 372

• Manufacturer Part Number: M306N4FGTFP#U0
• Description: MCU 5V 256K T-TEMP PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP#U0

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
23.6 Interrupts
23.6.1 Reading Address 00000h
23.6.2 Setting SP
23.6.3 NMI Interrupt
Do not read the address 00000h in a program. When a maskable interrupt request is accepted, the CPU
reads interrupt information (interrupt number and interrupt request priority level) from the address
00000h during the interrupt sequence. At this time, the IR bit for the accepted interrupt is set to 0.
If the address 00000h is read in a program, the IR bit for the interrupt which has the highest priority among
the enabled interrupts is set to 0. This causes a problem that the interrupt is canceled, or an unexpected
interrupt request is generated.
Set any value in the SP (USP, ISP) before accepting an interrupt. The SP (USP, ISP) is set to 0000h after
reset. Therefore, if an interrupt is accepted before setting any value in the SP (USP, ISP), the program
may go out of control.
Especially when using NMI interrupt, set a value in the ISP at the beginning of the program. For the first
and only the first instruction after reset, all interrupts including NMI interrupt are disabled.
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The NMI interrupt cannot be disabled. If this interrupt is unused, connect the NMI pin to VCC via a
resistor (pull-up).
The input level of the NMI pin can be read by accessing the P8_5 bit in the P8 register. Note that the
P8_5 bit can only be read when determining the pin level in NMI interrupt routine.
Stop mode cannot be entered into while input on the NMI pin is low. This is because while input on the
NMI pin is low the CM10 bit in the CM1 register is fixed to 0.
Do not go to wait mode while input on the NMI pin is low. This is because when input on the NMI pin
goes low, the CPU stops but CPU clock remains active; therefore, the current consumption in the chip
does not drop. In this case, normal condition is restored by an interrupt generated thereafter.
The low and high level durations of the input signal to the NMI pin must each be 2 CPU clock cycles +
300 ns or more.
Apr 14, 2006
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23. Usage Notes
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