M306N4FGTFP#U0 Renesas Electronics America, M306N4FGTFP#U0 Datasheet - Page 189

• Manufacturer Part Number: M306N4FGTFP#U0
• Description: MCU 5V 256K T-TEMP PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP#U0

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 15.20 Serial Data Logic Switching
Figure 15.21 TXD and RXD I/O Polarity Inverse
15.1.2.5 TXD and RXD I/O Polarity Inverse Function
15.1.2.4 Serial Data Logic Switching Function
This function inverses the polarities of the TXDi pin output and RXDi pin input. The logic levels of all input/output
data (including the start, stop and parity bits) are inversed.
Figure 15.21 shows the TXD and RXD I/O Polarity Inverse.
The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the
received data has its logic reversed when read from the UiRB register.
Figure 15.20 shows the Serial Data Logic Switching.
Apr 14, 2006
(1) When the UiLCH bit in the UiC1 register = 0 (no reverse)
(2) When the UiLCH bit = 1 (reverse)
i = 0 to 2
ST: Start bit
P: Parity bit
SP: Stop bit
NOTE:
(1) When the IOPOL bit in the UiMR register = 0 (no reverse)
Transfer clock
(2) When the IOPOL bit = 1 (reverse)
Transfer clock
Transfer clock
i = 0 to 2
ST: Start bit
P:
SP: Stop bit
NOTE:
Transfer clock
page 165 of 376
1. This applies to the case where the register bit are set as follows:
(no reverse)
(no reverse)
(no reverse)
(reverse)
1. This applies to the case where the register bits are set as follows:
Parity bit
(reverse)
(reverse)
PRYE bit in UiMR register = 1 (parity enabled)
CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge of the transfer clock)
UFORM bit in UiC0 register = 0 (LSB first)
STPS bit in UiMR register = 0 (1 stop bit)
TXDi
TXDi
UFORM bit in UiC0 register = 0 (LSB first)
STPS bit in UiMR register = 0 (1 stop bit)
PRYE bit in UiMR register = 1 (parity enabled)
RXDi
TXDi
RXDi
TXDi
"H"
"H"
"H"
"H"
"H"
"H"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"L"
"L"
"L"
"L"
"L"
"L"
ST
ST
ST
ST
ST
ST
D0
D0
D0
D0
D0
D0
D1
D1
D1
D1
D1
D1
D2
D2
D2
D2
D2
D2
D3
D3
D3
D3
D3
D3
D4
D4
D4
D4
D4
D4
D5
D5
D5
D5
D5
D5
D6
D6
D6
D6
D6
D6
D7
D7
D7
D7
D7
D7
P
P
P
P
P
P
SP
SP
SP
SP
SP
SP
15. Serial Interface