M306N4FGTFP#U0 Renesas Electronics America, M306N4FGTFP#U0 Datasheet - Page 151

• Manufacturer Part Number: M306N4FGTFP#U0
• Description: MCU 5V 256K T-TEMP PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP#U0

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Table 13.8 Pulse Period and Pulse Width Measurement Mode Specifications
i = 0 to 5
NOTES:
Count source
Count operation
Count start condition
Count stop condition
Interrupt request
generation timing
TBiIN pin function
Read from timer
Write to timer
13.2.3 Pulse Period and Pulse Width Measurement Mode
In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an
external signal. Table 13.8 lists the Pulse Period and Pulse Width Measurement Mode Specifications.
Figure 13.20 shows Registers TB0MR to TB5MR in Pulse Period and Pulse Width Measurement mode.
Figure 13.21 shows the Operation Timing when Measuring Pulse Period. Figure 13.22 shows the Operation
Timing when Measuring Pulse Width.
1.Bits TB0S to TB2S are assigned to bits 5 to 7 in the TABSR register, and bits TB3S to TB5S are
2. Interrupt request is not generated when the first effective edge is input after the timer started counting.
3. Value read from the TBi register is undefined until the second valid edge is input after the timer starts
assigned to bits 5 to 7 in the TBSR register.
counting.
Apr 14, 2006
Item
page 127 of 376
f1, f2, f8, f32, fC32
• Up-count
• Counter value is transferred to reload register at an effective edge of
Set the TBiS bit
Set the TBiS bit to 0 (count stops)
• When an effective edge of measurement pulse is input
• Timer overflow. If an overflow occurs, the MR3 bit in the TBiMR register
Measurement pulse input
Contents of the reload register (measurement result) can be read by reading
TBi register
Value written to the TBi register is written to neither reload register nor counter
measurement pulse. The counter value is set to 0000h to continue counting.
is set to 1 (overflow) simultaneously. The MR3 bit is set to 0 (no overflow)
by writing to the TBiMR register at the next count timing or later after the
MR3 bit was set to 1. At this time, make sure the TBiS bit is set to 1
(count starts).
(3)
(1)
to 1 (count starts)
Specification
(2)
13. Timers