M306N4FGTFP#U0 Renesas Electronics America, M306N4FGTFP#U0 Datasheet - Page 391

• Manufacturer Part Number: M306N4FGTFP#U0
• Description: MCU 5V 256K T-TEMP PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP#U0

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
23.12 Programmable I/O Ports
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase
output forcible cutoff by input on NMI pin enabled), pins P7_2 to P7_5, P8_0, and P8_1 go to a
high-impedance state.
Setting the SM32 bit in the S3C register to 1 causes the P9_2 pin to go to a high-impedance state.
The input threshold voltage of pins differs between programmable I/O ports and peripheral functions.
Therefore, if any pin is shared by a programmable I/O port and a peripheral function and the input level at
this pin is outside the range of recommended operating conditions VIH and VIL (neither “high” nor “low”),
the input level may be determined differently depending on which side—the programmable I/O port or the
peripheral function—is currently selected.
Undefined values are read from bits P3_7 to P3_4, and PD3_7 to PD3_4 by reading registers P3 and PD3
when bits PM01 to PM00 in the PM0 register are set to 01b (memory expansion mode) or 11b (microprocessor
mode) and setting the PM11 bit to 1.
Use the MOV instruction when rewriting registers P3 and PD3 (including the case that the size specifier is
“.W” and registers P2 and PD2 are rewritten).
When bits PM01 to PM00 are rewritten, “L” is output from pins P3_7 to P3_4 during 0.5 cycles of the BCLK
by setting bits PM01 to PM00 in the PM0 register to 01b (memory expansion mode) or 11b (microprocessor
mode) from 00b (single-chip mode) after setting the PM11 bit to 1.
Apr 14, 2006
page 367 of 376
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23. Usage Notes