M306N4FGTFP#U0 Renesas Electronics America, M306N4FGTFP#U0 Datasheet - Page 153

• Manufacturer Part Number: M306N4FGTFP#U0
• Description: MCU 5V 256K T-TEMP PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP#U0

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 13.22 Operation Timing When Measuring Pulse Width
Figure 13.21 Operation Timing When Measuring Pulse Period
Apr 14, 2006
Reload register
transfer timing
Measurement pulse
Timing at which counter
reaches 0000h
TBiS bit
MR3 bit in
TBiMR register
i = 0 to 5
NOTES:
Count source
IR bit in
TBiIC register
IR bit in
TBiIC register
MR3 bit in
TBiMR register
Reload register
transfer timing
TBiS bit
i = 0 to 5
NOTES:
Count source
Measurement pulse
Timing at which counter
reaches 0000h
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where bits MR1 to MR0 in the TBiMR register are 00b (measure the interval
from falling edge to falling edge of the measurement pulse).
1. Counter is initialized at completion of measurement.
2. Timer has overflowed.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are 10b (measure the
interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge
of the measurement pulse).
Bits TB0S to TB2S are assigned to bits 5 to 7 in the TABSR register, and bits TB3S to TB5S are
assigned to bits 5 to 7 in the TBSR register.
Bits TB0S to TB2S are assigned to bits 5 to 7 in the TABSR register, and bits TB3S to TB5S are
assigned to bits 5 to 7 in the TBSR register.
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counter
counter
"H"
"L"
1
0
1
0
1
0
"H"
"L"
0
0
0
1
1
1
Set to 0 upon accepting an interrupt request or by writing in program
Set to 0 upon accepting an interrupt request or by
writing in program
Transfer
(undefined
value)
(NOTE 1)
Transfer
(undefined value)
(NOTE 1)
Transfer
(measured value)
(NOTE 1)
Transfer
(measured
value)
(NOTE 1)
Transfer
(measured value)
(NOTE 1)
Transfer
(measured value)
(NOTE 1)
(NOTE 2)
(NOTE 2)
13. Timers