M306N4FGTFP#U0 Renesas Electronics America, M306N4FGTFP#U0 Datasheet - Page 252

• Manufacturer Part Number: M306N4FGTFP#U0
• Description: MCU 5V 256K T-TEMP PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP#U0

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
19.6 CAN Module System Clock Configuration
Figure 19.14 CAN Module System Clock Generation Circuit Block Diagram
19.7 Bit Timing Configuration
Figure 19.15 Bit Timing
The M16C/6N Group (M16C/6N4) has a CAN module system clock select circuit.
Configuration of the CAN module system clock can be done through manipulating the CCLKR register and
the BRP bit in the CiCONR register (i = 0, 1).
For the CCLKR register, refer to 8. Clock Generation Circuit.
Figure 19.14 shows the CAN Module System Clock Generation Circuit Block Diagram.
The bit time consists of the following four segments:
Figure 19.15 shows the Bit Timing.
• Synchronization segment (SS)
• Propagation time segment (PTS)
• Phase buffer segment 1 (PBS1)
• Phase buffer segment 2 (PBS2)
The range of each segment: Bit time = 8 to 25Tq
This serves for monitoring a falling edge for synchronization.
This segment absorbs physical delay on the CAN network which amounts to double the total sum of
delay on the CAN bus, the input comparator delay, and the output driver delay.
This serves for compensating the phase error. When the falling edge of the bit falls later than expected,
the segment can become longer by the maximum of the value defined in SJW.
This segment has the same function as the phase buffer segment 1. When the falling edge of the bit
falls earlier than expected, the segment can become shorter by the maximum of the value defined in SJW.
Apr 14, 2006
f1
fCAN
P
fCANCLK : CAN communication clock fCANCLK = fCAN/2(P + 1)
page 228 of 376
SS
CCLKR register
Value: 1, 2, 4, 8, 16
: CAN module system clock
: The value written in the BRP bit in the CiCONR register ( i = 0, 1). P = 0 to 15
CAN module
system clock
divider
SS = 1Tq
PTS = 1Tq to 8Tq
PBS1 = 2Tq to 8Tq
PBS2 = 2Tq to 8Tq
SJW = 1Tq to 4Tq
PTS
Divide-by-1 (undivided)
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
Bit time
PBS1
Configuration of PBS1 and PBS2: PBS1 ≥ PBS2
SJW
fCAN
Sampling point
Prescaler
1/2
PBS2
CAN module
division value
SJW
Baud rate
prescaler
: P + 1
PBS1 ≥ SJW
PBS2 ≥ 2 when SJW = 1
PBS2 ≥ SJW when 2 ≤ SJW ≤ 4
fCANCLK
19. CAN Module