M306N4FGTFP#U0 Renesas Electronics America, M306N4FGTFP#U0 Datasheet - Page 384

• Manufacturer Part Number: M306N4FGTFP#U0
• Description: MCU 5V 256K T-TEMP PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP#U0

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
23.10 A/D Converter
Figure 23.2 Use of Capacitors to Reduce Noise
Set the ADCON0 (except bit 6), registers ADCON1 and ADCON2 when A/D conversion is stopped (before
a trigger occurs). After stopping A/D conversion, the VCUT bit in the ADCON1 register is changed from 1
(VREF connected) to 0 (VREF not connected),
When the VCUT bit is changed from 0 to 1, start A/D conversion after passing 1 µs or longer.
To prevent noise-induced device malfunction or latch-up, as well as to reduce conversion errors, insert
capacitors between the AVCC, VREF, and analog input pins (ANi (i = 0 to 7), AN0_i, and AN2_i) each and
the AVSS pin. Similarly, insert a capacitor between the VCC pin and the VSS pin.
Figure 23.2 shows the Use of Capacitors to Reduce Noise.
Make sure the port direction bits for those pins that are used as analog inputs are set to 0 (input mode).
Also, if the TGR bit in the ADCON0 register = 1 (external trigger), make sure the port direction bit for the
__________
ADTRG pin is set to 0 (input mode).
When using key input interrupt, do not use any of four pins AN4 to AN7 as analog inputs. (A key input
interrupt request is generated when the A/D input voltage goes low.)
The φAD frequency must be 10 MHz or less. Without sample and hold, limit the φAD frequency to 250 kHz
or more. With the sample and hold, limit the φAD frequency to 1 MHz or more.
When changing an A/D operating mode, select analog input pin again in bits CH2 to CH0 in the ADCON0
register and bits SCAN1 to SCAN0 in the ADCON1 register.
Apr 14, 2006
page 360 of 376
ANi: ANi, AN0_i, and AN2_i (i =0 to 7)
NOTES:
C4
1. C1 ≥ 0.47 µF, C2 ≥ 0.47 µF, C3 ≥ 100 pF, C4 ≥ 0.1 µF (reference).
2. Use thick and shortest possible wiring to connect capacitors.
VCC
VSS
MCU
AVCC
VREF
AVSS
ANi
C1
C2
C3
23. Usage Notes