M306N4FGTFP#U0 Renesas Electronics America, M306N4FGTFP#U0 Datasheet - Page 288

• Manufacturer Part Number: M306N4FGTFP#U0
• Description: MCU 5V 256K T-TEMP PB-FREE 100-Q
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGTFP#U0

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Table 21.4 Software Commands
SRD:data in the SRD register (D7 to D0)
WA: Address to be written (The address specified in the first bus cycle is the same even address as the
WD: 16-bit write data
BA: Highest-order block address (must be an even address)
✕:
xx:
NOTE:
Read array
Read status register
Clear status register
Program
Block erase
Erase all unlocked block
Lock bit program
Read lock bit status
21.3.5 Software Commands
Software commands are described below. The command code and data must be read and written in 16-bit
unit, to and from even addresses in the user ROM area. When writing command code, the high-order 8
bits (D15 to D8) are ignored.
Table 21.4 lists the Software Commands.
1. Blocks 0 to 8 can be erased by the erase all unlocked block command.
21.3.5.1 Read Array Command (FFh)
21.3.5.2 Read Status Register Command (70h)
21.3.5.3 Clear Status Register Command (50h)
The read array command reads the flash memory.
By writing command code xxFFh in the first bus cycle, read array mode is entered. Content of a speci-
fied address can be read in 16-bit unit after the next bus cycle.
The MCU remains in read array mode until another command is written. Therefore, contents from multiple
addresses can be read consecutively.
The read status register command reads the status register (refer to 21.3.7 Status Register (SRD
Register) for detail).
By writing command code xx70h in the first bus cycle, the status register can be read in the second bus
cycle. Read an even address in the user ROM area.
Do not execute this command in EW1 mode.
The clear status register command clears the status register.
By writing xx50h in the first bus cycle, bits FMR07 to FMR06 in the FMR0 register are set to 00b and bits
SR5 to SR4 in the status register are set to 00b.
address specified in the second bus cycle.)
Given even address in the user ROM area
High-order 8 bits of command code (ignored)
Block A cannot be erased. The block erase command must be used to erase the block A.
Apr 14, 2006
Software Command
page 264 of 376
(1)
Mode
Write
Write
Write
Write
Write
Write
Write
Write
First Bus Cycle
Address
WA
BA
✕
✕
✕
✕
✕
✕
(D15 to D0)
xxFFh
xxA7h
xx70h
xx50h
xx40h
xx20h
xx77h
xx71h
Data
Mode
Read
Write
Write
Write
Write
Write
-
-
Second Bus Cycle
21. Flash Memory Version
Address
WA
BA
BA
BA
✕
✕
-
-
(D15 to D0)
xxD0h
xxD0h
xxD0h
xxD0h
Data
SRD
WD
-
-