ATSAM3S4CA-AU Atmel, ATSAM3S4CA-AU Datasheet - Page 770

• Manufacturer Part Number: ATSAM3S4CA-AU
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 79
• Ram Memory Size: 48KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Cpu Family: AT91
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 64MHz
• Total Internal Ram Size: 48KB
• # I/os (max): 79
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.62V
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

34.7.2
Name:
Addresses:
Access:
This register can only be written if the WPEN bit is cleared in
• TC0XC0S: External Clock Signal 0 Selection
• TC1XC1S: External Clock Signal 1 Selection
• TC2XC2S: External Clock Signal 2 Selection
• QDEN: Quadrature Decoder ENabled
0 = disabled.
1 = enables the quadrature decoder logic (filter, edge detection and quadrature decoding).
quadrature decoding (direction change) can be disabled using QDTRANS bit.
770
Value
Value
Value
INVIDX
0
1
2
3
0
1
2
3
0
1
2
3
31
23
15
–
7
–
SAM3S Preliminary
TC Block Mode Register
Name
TCLK0
–
TIOA1
TIOA2
Name
TCLK1
–
TIOA0
TIOA2
Name
TCLK2
–
TIOA1
TIOA2
INVB
30
22
14
TC_BMR
0x400100C4 (0), 0x400140C4 (1)
Read-write
–
6
–
MAXFILT
Description
Signal connected to XC0: TCLK0
Reserved
Signal connected to XC0: TIOA1
Signal connected to XC0: TIOA2
Description
Signal connected to XC1: TCLK1
Reserved
Signal connected to XC1: TIOA0
Signal connected to XC1: TIOA2
Description
Signal connected to XC2: TCLK2
Reserved
Signal connected to XC2: TIOA1
Signal connected to XC2: TIOA2
INVA
29
21
13
–
5
TC2XC2S
EDGPHA
28
20
12
–
4
“TC Write Protect Mode Register” on page
QDTRANS
FILTER
27
19
11
–
3
TC1XC1S
SPEEDEN
26
18
10
–
–
2
IDXPHB
POSEN
25
17
9
1
TC0XC0S
MAXFILT
6500C–ATARM–8-Feb-11
778.
SWAP
QDEN
24
16
8
0