ATSAM3S4CA-AU Atmel, ATSAM3S4CA-AU Datasheet - Page 373

• Manufacturer Part Number: ATSAM3S4CA-AU
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 79
• Ram Memory Size: 48KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Cpu Family: AT91
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 64MHz
• Total Internal Ram Size: 48KB
• # I/os (max): 79
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.62V
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

23.8.3.3
23.8.3.4
23.8.3.5
6500C–ATARM–8-Feb-11
Null Delay Setup and Hold
Null Pulse
Write Cycle
The write_cycle time is defined as the total duration of the write cycle, that is, from the time
where address is set on the address bus to the point where address may change. The total write
cycle time is equal to:
NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD
= NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD
All NWE and NCS (write) timings are defined separately for each chip select as an integer num-
ber of Master Clock cycles. To ensure that the NWE and NCS timings are coherent, the user
must define the total write cycle instead of the hold timing. This implicitly defines the NWE hold
time and NCS (write) hold times as:
NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE
NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE
If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active
continuously in case of consecutive write cycles in the same memory (see
ever, for devices that perform write operations on the rising edge of NWE or NCS, such as
SRAM, either a setup or a hold must be programmed.
Figure 23-10. Null Setup and Hold Values of NCS and NWE in Write Cycle
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to
unpredictable behavior.
A [23:0]
D[7:0]
NWE
MCK
NCS
NCS_WR_PULSE
NWE_PULSE
NWE_CYCLE
NCS_WR_PULSE
NWE_CYCLE
NWE_PULSE
SAM3S Preliminary
NCS_WR_PULSE
NWE_CYCLE
NWE_PULSE
Figure
23-10). How-
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