ATSAM3S4CA-AU Atmel, ATSAM3S4CA-AU Datasheet - Page 761

• Manufacturer Part Number: ATSAM3S4CA-AU
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 79
• Ram Memory Size: 48KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Cpu Family: AT91
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 64MHz
• Total Internal Ram Size: 48KB
• # I/os (max): 79
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.62V
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 34-15. Predefined Connection of the Quadrature Decoder with Timer Counters
34.6.14.2
6500C–ATARM–8-Feb-11
TIOA0
TIOB0
TIOB1
Input Pre-processing
PHA
PHB
IDX
(Filter + Edge
Detect + QD)
Quadrature
Decoder
Interruptions can be generated on different events.
A compare function (using TC_RC register) is available on channel 0 (speed/position) or chan-
nel 1 (rotation) and can generate an interrupt by means of the CPCS flag in the TC_SR
registers.
Input pre-processing consists of capabilities to take into account rotary sensor factors such as
polarities and phase definition followed by configurable digital filtering.
Each input can be negated and swapping PHA, PHB is also configurable.
PHEdges
Index
Direction
TIOA0
TIOB0
TIOB1
1
QDEN
SPEEDEN
1
1
1
QDEN
TIOA
TIOB
XC0
TIOB
XC0
1
1
SAM3S Preliminary
Reset pulse
XC0
XC0
Speed Time Base
Timer/Counter
Channel 0
Speed/Position
Timer/Counter
Channel 1
Rotation
Timer/Counter
Channel 2
761