ATSAM3S4CA-AU Atmel, ATSAM3S4CA-AU Datasheet - Page 447

• Manufacturer Part Number: ATSAM3S4CA-AU
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 79
• Ram Memory Size: 48KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Cpu Family: AT91
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 64MHz
• Total Internal Ram Size: 48KB
• # I/os (max): 79
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.62V
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

26.16.4
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
• PIDx: Peripheral Clock x Enable
0 = No effect.
1 = Enables the corresponding peripheral clock.
Note:
Note:
6500C–ATARM–8-Feb-11
PID31
PID23
PID15
PID7
31
23
15
7
PID2 to PID31 refer to identifiers as defined in the section “Peripheral Identifiers” in the product datasheet. Other peripherals
can be enabled in PMC_PCER1.
Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC.
PMC Peripheral Clock Enable Register 0
PMC_PCER0
0x400E0410
Write-only
PID30
PID22
PID14
PID6
30
22
14
6
PID29
PID21
PID13
PID5
29
21
13
5
PID28
PID20
PID12
PID4
28
20
12
4
“PMC Write Protect Mode Register” on page
PID27
PID19
PID11
PID3
27
19
11
3
PID26
PID18
PID10
PID2
26
18
10
2
SAM3S Preliminary
PID25
PID17
PID9
25
17
–
9
1
466.
PID24
PID16
PID8
24
16
–
8
0
447