ATMEGA128-16MN Atmel, ATMEGA128-16MN Datasheet - Page 94
![MCU AVR 128KB FLASH 16MHZ 64QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATMEGA128-16MN
Manufacturer Part Number
ATMEGA128-16MN
Description
MCU AVR 128KB FLASH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128-16MN
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Output Compare
Unit
94
ATmega128
Signal description (internal signals):
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the clock select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the
timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of
whether clk
count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in
the Timer/Counter Control Register (TCCR0). There are close connections between how the
counter behaves (counts) and how waveforms are generated on the output compare output
OC0. For more details about advanced counting sequences and waveform generation, see
“Modes of Operation” on page
The Timer/Counter overflow (TOV0) flag is set according to the mode of operation selected by
the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.
The 8-bit comparator continuously compares TCNT0 with the Output Compare Register
(OCR0). Whenever TCNT0 equals OCR0, the comparator signals a match. A match will set the
output compare flag (OCF0) at the next timer clock cycle. If enabled (OCIE0 = 1), the output
compare flag generates an output compare interrupt. The OCF0 flag is automatically cleared
when the interrupt is executed. Alternatively, the OCF0 flag can be cleared by software by writ-
ing a logical one to its I/O bit location. The waveform generator uses the match signal to
generate an output according to operating mode set by the WGM01:0 bits and compare output
mode (COM01:0) bits. The max and bottom signals are used by the waveform generator for han-
dling the special cases of the extreme values in some modes of operation
on page
count
direction
clear
clk
top
bottom
T0
97).
T0
Figure 36
Increment or decrement TCNT0 by 1.
Selects between increment and decrement.
Clear TCNT0 (set all bits to zero).
Timer/Counter clock.
Signalizes that TCNT0 has reached maximum value.
Signalizes that TCNT0 has reached minimum value (zero).
is present or not. A CPU write overrides (has priority over) all counter clear or
shows a block diagram of the output compare unit.
T0
). clk
97.
T0
can be generated from an external or internal clock source,
(“Modes of Operation”
2467V–AVR–02/11
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