ATMEGA128-16MN Atmel, ATMEGA128-16MN Datasheet - Page 105

• Manufacturer Part Number: ATMEGA128-16MN
• Description: MCU AVR 128KB FLASH 16MHZ 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128-16MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timer/Counter
Register – TCNT0
Output Compare
Register – OCR0
2467V–AVR–02/11
Table 55. Compare Output Mode, Phase Correct PWM Mode
Note:
• Bit 2:0 – CS02:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see
56.
Table 56. Clock Select Bit Description
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare
match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a compare match between TCNT0 and the OCR0 Register.
The Output Compare Register contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an output compare interrupt, or to
generate a waveform output on the OC0 pin.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
COM01
CS02
0
0
1
1
0
0
0
0
1
1
1
1
1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the compare
COM00
match is ignored, but the set or clear is done at TOP. See
100
CS01
0
1
0
1
R/W
R/W
for more details.
0
0
1
1
0
0
1
1
7
0
7
0
Description
Normal port operation, OC0 disconnected.
Reserved
Clear OC0 on compare match when up-counting. Set OC0 on compare
match when downcounting.
Set OC0 on compare match when up-counting. Clear OC0 on compare
match when downcounting.
R/W
R/W
6
0
6
0
CS00
0
1
0
1
0
1
0
1
R/W
R/W
5
0
5
0
Description
No clock source (Timer/Counter stopped)
clk
clk
clk
clk
clk
clk
clk
T
T
T0S
T0S
T0S
T0S
T0S
0
0
S
S
/256 (From prescaler)
/1024 (From prescaler)
R/W
R/W
/(No prescaling)
/8 (From prescaler)
/32 (From prescaler)
/64 (From prescaler)
/128 (From prescaler)
4
0
4
0
TCNT0[7:0]
OCR0[7:0]
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
(1)
“Phase Correct PWM Mode” on page
R/W
R/W
1
0
1
0
R/W
R/W
ATmega128
0
0
0
0
TCNT0
OCR0
Table
105